> The INTC has 2 operation modes: SW vector mode and HW vector mode. The HW
> vector mode is the same like the ISRs handling is realized on almost all MCUs.
With the exception of most Power PCs. They only have one hardware request line into the core,and have traditionally only had one interrupt vector and service routine for this interrupt. This code always reads a vector register in the interrupt controller and then vectors in software.
If you read through the core manual in detail you'll also find that "unlike most old CPUs" the CPU registers aren't saved on a stack automatically. Only the PC is saved and the service routine has to do all the stacking itself, in code. Likewise, the MMU is mainly software. All the MMU table walking has to be done in software.
There's a reason for this. Software is cheaper than hardware, and at one operation per clock is as fast as hardware too.
> This all work will increase the interrupt latency,
To a first approximation it probably doesn't. It can even reduce the latency as one small handler is more likely to be in the instruction cache than a whole array of them.
What it does allow more easily is to have both "fast interrupts" and "slow interrupts" like some older CPUs had, where the "fast" ones don't stack the registers and the "slow ones" did. This can be emulated in code with this "hardware mode" and it would save a few instructions and a few nanoseconds.
It does look like Freescale have enhanced these chips to add "hardware vectored interrupts", but from the MPC5604 manual:
16.4.1.2 Hardware vector mode
In hardware vector mode, the hardware is the interrupt vector
signal from the INTC in conjunction with a processor with the
capability use that vector.
This feature depends on the "capability use that vector" [sic]. The MPC5604 manual doesn't detail much about this mode. Maybe the MPC560x chips don't support it?
In contrast, the MPC564x and MPC5668x manuals go into a great deal of detail about how the hardware mode works. If you're not reading these manuals then I suggest you do, even if you're not using these chips.
The trade off is that these chips need a lot of interrupt prologue and epilogue code. With software mode you only have to store that once, and then the code vectors off to the individual handlers. In hardware mode, all that prologue code needs to e duplicated (you'd have them all branch to a common epilogue though). You have a choice. Which one you choose to use will depend on what you need to do. I's suggest you benchmark and measure both approaches before making a decision.
The chip supports both so it can run code written for older CPUs.
Tom
