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GPIO Pin during reset

Question asked by Mathias Beck on Apr 12, 2012
Latest reply on Apr 13, 2012 by Mathias Beck

Hi all


On the project I am working at the moment I am using a MCF5373L processor.

At the beginning the processor stays in reset until a switch desactivate the reset. The switch is connected to the processor (pin FB_CS5, functions of the the switch are used when processor is running) and a CPLD (function of the switch is desactivating of the reset).


Found in a thread and also in the Reference Manual, the GPIO are digitial inputs. In the thread is written that a weak pull up is enabled during the reset.




When I press now the button (connected over a PU to 3.3V to GND --> Low active), the signal which is connected to the CF and the CPLD only sinks from 3.3V to arround 3.1V.


I tried the same without CPLD (when the button is only connected to the CF) and the result is the same.


As it looks like, the GPIO are driven activly high during the reset. But I could not find a proper answer on that neither in the Reference Manual, nor in the Datasheet nor in the forum.


Is it like that and are there any possibilitys to change that? As I saw in the posted thread, there is no configuration register for that.


Thank you for helping!