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MPC5668 does not support inter-core exclusive access to shared memory through CAS primitive??

Question asked by gang han on Apr 2, 2012
Latest reply on Apr 5, 2012 by TomE

Recently, I implemented a CAS(compare and swap) based on PowerPC instruction lwarx and stwcx as an inline assembly function.

However, it turns out only the intra-core memory synchronization is supported, while the inter-core one is not. Then, I looked through almost all the related documents to find below information. 

1 In e200z6 PowerPCTM Core Reference Manual pp124

Reservation granularity is implementation dependent. The e200z6 does not define a reservation granule explicitly; it is defined by external logic. When no external logic is provided, the e200z6 does not compare addresses; thus, the effective implementation granularity is null.


2 In PowerPC Microprocessor Family: The Programming Environments Manual for 64-bit Microprocessors pp423
     When the RESERVE bit is set, the processor enables hardware snooping for the block of memory addressed
     by the RESERVE address.
      If the processor detects that another processor writes to the block of memory it
     has reserved, it clears the RESERVE bit.


3 However, I found this in MPC5668x Microcontroller Reference Manual pp364

     Reservation management logic external to the e200z6 is not implemented.


Who can help me, please?