I'm creating a UART driver and had intially disabled the FIFO buffers at first. I was only receiving the first of 5 bytes of data.
I eventually decided to try and enable the FIFO buffers and find that ALL of the expected 5 bytes are present during my first interrupt.
How can this be if I'm running my core clock at 100MHz? My MCU should be fast enough to get the interrupt after the first byte, pull the byte out of the buffer, increment the counter, and then go about it's business long before the 2nd byte arrives. Am I wrong here?
Note: I'm using UART 1.