I am attempting to configure the SDRAM Controller. I believe that I have to use a CL of 3. What do I use in the RD_LAT field of the SDCFG1 register?
Table 18-9. SDCFG1 Field DescriptionsRead CAS Latency. Read command to read data available delay counter.For DDR: If CL = 2, write 0x6 If CL = 2.5, write 0x7For SDR: If CL = 2, write 0x2 If CL = 3, write 0x3
So for DDR it looks like "6, 7, 8, 9" would get you "2, 2.5, 3, 3.5". The fact that they don't list above 2.5 might mean it isn't supported or it might mean it isn't necessary.
Why do you think you need a CL of 3? The memory clock (60 or 80MHz) is a lot slower than the DDR chips are normally run at, so you should be able to run with a low CL.
For instance, I'm looking at a data sheet for an ISSI IS43/46R86400D.
It can run at CL=2 up to 133MHz, CL=2.5 up to 167MHz and only needs CL=3 for speeds above 167MHz (200MHz or 250MHz depending on the speed grade).
So I think you should be able to run with CL=2, and as long as you programing a matching CL into SDCFG1 and to the SDRAM Mode register via the SDMR it should work fine.
Don't forget the MSCR_SDRAM registers. Search this forum for "MSCR_SDRAM" to fnd my previous posts.
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