Posted: Jul 16, 2004 - 03:23 AM
I have new to this group.
I am working on HC(s)08 MCU and using CW for code developement.
I wanted to know what should be done in case I want serial communication interrupt to be active inside a timer ISR handler.
Thanks In advance.
Posted: Jul 16, 2004 - 06:00 AM
Try to create a new project using the project Wizard, make sure you enable Processor Expert.
Then add a TimerInt and a AsyncroSerial bean to your project (in Processor Expert).
Adjust the properties and methods to whatever you wish to use and the tool will generate code for you .
Posted: Jul 16, 2004 - 06:57 AM
But I do not want to use the processor expert. In that case how could it be possible through code to keep my serial interrupt at higher priority than timer interrupt. This is because the Timer overflow interrupt has higher priority than serial interrupt by default.
Posted: Jul 16, 2004 - 07:15 AM
I don't know this processor but there may be some registers to configure the priority of interrupts. You must write into these registers.
Posted: Jul 20, 2004 - 06:52 PM
This is 4 days old so you've probably already found a solution, but....
Since the interrupt mask bit is automatically set in an ISR (masking ALL interrupt sources) you can clear the interrupt mask bit at the top of your timer ISR which will allow other interrupt sources to interrupt your interrupt. As long as your other ISRs, and the timer ISR itself, can execute prior to the next timer ISR you can get away with this and live. I hope this was the answer you were looking for.
Posted: Jul 23, 2004 - 02:24 PM
Thanks for the reply to my querry regarding the interrupts,....Actually I got it while going thru the data sheet of HCS08....
Now I have another problem .,
I want to write to non volatile registers of HCS08 at run time.
How can I do that and is it possible?
Posted: Jul 26, 2004 - 05:31 AM
In fact the HC08 CPU does not support nested interrupt.
Any manipulation you would make to enable nested interrupt may result in nasty side effect.
Basically the current interrupt must terminate before the CPU can service another one.
Posted: Jul 26, 2004 - 10:07 AM
I think Nested interrupts can be supported but it should be ensured that the the I bit in the CCR register of the CPU is cleared. But this is not suggested as debugging becomes difficult in case of Errors.
Posted: Jul 27, 2004 - 04:53 AM
From the HCS08 user manual from Freescale:
"While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0 when the CCR is restored from the value that was stacked on entry to the ISR.
In rare cases, the I bit may be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug."
Basically you can use nested interrupt, but in this case implementation of the proper interrupt mechanism must be managed by the programmer.