> I am using a MCF5329 and two IS43R1632D DDR SDRAM chips
DDR mode. That means you have the two chips on a 16-bit data bus using SD_CS0 and SD_CS1.
I can't find the data sheet for that part. You're using IS43R16320D parts.
512 Mbit, so 32M by 16 or 64MByte each. So the chip selects have to be set up 64M apart:
>>> mem write32 0xFC0B8110 0x40000019 ; SDCS0
>>> mem write32 0xFC0B8114 0x44000019 ; SDCS1
That's correct.
The chips are 8M by 16 by 4 banks with 8k rows (A0-A12, 13 bit) and 1k columns (A0-A9, 10 bits).
From the MCF5329 Reference Manual that matches 512M - 32M * 16bit - 13 * 10 * 4, and SDCR[ADDR_MUX] = 01
>>> mem write32 0xFC0B8004 0xe1462c02 ; SDCR, (IPALL)
>>> ...
>>> mem write32 0xFC0B8004 0x71462c00 ; SDCR, (REF_EN)
The second digit is a "1" so the address mux is set up OK. The first digit being "7" has the DDR bit set, so that's OK. The 5th digit is "2" which is 16 bit data bus.
Check you have the DRAMSEL pin strapped to ground.
Nothing explaining the 2k boundary yet. What SORT of memory errors is it giving, or is it a dumb test giving "pass/fail"?
Do you say it won't WORK with a block size over 2k or it won't FAIL with it over 2K? This isn't clear.
From the Reference Manual Table 18-3. Addresses A9-A2 are connected to the CA lines, A111-A10 to the BA lines and A23-A12 to the RA lines. So if it is going haywire at 2k that suggests your BA0 and BA1 lines aren't working.
> Why would the test fail two or three times and then start working?
That's happened to me and to other people. Look in my "bit rot" post below where I mention this. The memory has to be READ (possibly BURST READ using a MOVEM.L or with the cache enabled) a few times before you "read it for real" or the first burst read returns corrupted data. To be sure I burst read and burst write for a while after SDRAM initialisation. Something in the SDRAM chip needs "pumping up" before it works properly. You can write all you like to it (we copy 1M from FLASH to DRAM) and then the first read returns garbage and subsequent ones are OK.
Check the DRIVE STRENGTH programming. Read here for details:
https://community.freescale.com/message/66587#66587
Your provided initialisation file doesn't write to MSCR_FLEXBUS and MSCR_SDRAM. These default to "high strength" which is only OK if you've got a bus-and-socket system with terminators everywhere. For a "minimal system" you may have to program MSCR_SDRAM to lower than "full strength". The manual is wrong with the documentation of these registers, read my post above.
Check this stuff I've written here before:
https://community.freescale.com/message/84108#84108
