Gurunath Salgar

MC9S12GRMV1: How simultaneous P-Flash and EEPROM Operations are allowed

Discussion created by Gurunath Salgar on Jan 9, 2012
Latest reply on Jan 9, 2012 by HSW

Hello Friends,

 

Query Description: 

I am looking into the possibility of parallel/simultaneous execution of CPU & Memory Controller.

I am refering into MC9S12GRMV1.pdf for my analysis.

I am referring two sections,

26.1.3 Block Diagram, Page no. 853

26.4.5 Allowed Simultaneous P-Flash and EEPROM Operations, Page no. 882

 

The block diagram shows that the 16 bit internal bus is shared between CPU & memory controller.

Table mentioned in 26.4.5 says that Program_Flash_Read is possible when we do Data_Flash_MarginRead, Data_Flash_Program, Data_Flash_SectorErase.

I having an scenario in which I have to erase the sector in Data_Flash.

During erase, asynchronously I want to execute the program on CPU by reading the instructions from Program_Flash.

That means Data_Flash erase is happening in polling mode.

Table mentioned in 26.4.5 says that it's possible, however after looking into the 26.1.3 Block Diagram (Shared Bus), I got confused.

 

Query:

1. How the simultaneous execution on CPU & memory controller is possible if they both are using the same internal bus.

2. If simulatanous execution is not possible, then where the "26.4.5 Allowed Simultaneous P-Flash and EEPROM Operations" will be applicable?

 

I have attached the datasheet with this post.

Please let me know, incase any additional information is required.

 

Thanks in Advance.

 

- GURU

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