Tim Watko

Chip select problem on 5329

Discussion created by Tim Watko on Jan 4, 2012
Latest reply on Jan 6, 2012 by TomE

I am having a problem on a new board with the chip selects. I have a MCF5329 board and a P E BDM pod. Just using the memory windows of the ColdFire Debugger, I am configuring chip selects 0, 1 and 2. When I set bytes in the chip select 1 and 2 areas, chip select 0 also activates. Here are the chip select configurations:

       CSAR0 0

       CSMR0 0x00ff 0001

       CSCR0 0x0000 17a0

       CSAR1 0x1000 0000

       CSMR1 0x0003 0001

       CSCR1 0x0000 1ba0

       CSAR2 0x2000 0000

       CSMR2 0x00ff 0001

       CSCR2 0x0000 0ba0


CS0 is for 16 MB of Flash, 5 wait states, base address 0

CS1 is for 256 KB of Static RAM, 6 wait states, base address 0x1000 0000

CS2 is for for an FPGA, 2 wait states, base address 0x2000 0000


After configuring the chip selects, If I write to location 0x1000 0000, both chip selects 0 and 1 go active, CS1 for one pulse and CS0 for 2 pulses. If I write to location 0x200d 0000, both chip selects 0 and 2 go active. Once again, I am using the ColdFire debugger to modify the memory. These memory regions do not overlap, so I don't understand why CS0 goes active. What am I doing wrong?