MCIMX6ULL-EVK DDR3 length

[Sylvain1408]

Hello,

I am currently designing a pcb with the i.MX6ULL.

I went through the EVK concerning the DDR3 match length to check the rules and found that ADDR bank were splitted between top and bottom layer. Respectively 1,2,3,5,6,9,14 on top and 0,4,7,8,10,11,12,13,15 on bottom.

The length on constraint manager shows that they should be between 34.92 and 36.19mm which is good for all of them.

Except the fact that for those on bottom, the 2 via length are not taken into account, which add +2mm for each signal. How's that correct?

What am i missing?

Thanks,

Sylvain

[weidong_sun]

Hi,

 It is no problem to add +2mm for each signal.

weidong

[Sylvain1408]

Hello Weidong,

Thanks for answering.

I don't get why it is not a problem. Adding 2mm overall yes, but adding only for certain address signals it seems it broke the matched length rules specified in the hardware design guide.

What do you think?

Thanks,

Sylvain