Below are the patches to support SDIO-UART 8987 M2 module on mek_8q M2 port. After applying the patches, PCIe chip can't be recognized on M2 port. Revert the patches if want to use PCIe chip. Patches are from Andy Duan.
--- a/board/freescale/imx8qm_mek/imx8qm_mek.c
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -373,6 +373,7 @@ int board_init(void)
#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC)
setup_typec();
#endif
+ sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R3, SC_PM_PW_MODE_ON);
#ifdef CONFIG_SNVS_SEC_SC_AUTO
{
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -151,6 +151,11 @@
};
+ usdhc3_pwrseq: usdhc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+
epdev_on: fixedregulator@100 {
compatible = "regulator-fixed";
pinctrl-names = "default", "sleep";
@@ -159,8 +164,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "epdev_on";
- gpio = <&lsio_gpio1 13 0>;
- enable-active-high;
};
reg_fec2_supply: fec2_nvcc {
@@ -1036,6 +1039,22 @@
status = "okay";
};
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>;
+ bus-width = <4>;
+ pinctrl-assert-gpios = <&lsio_gpio4 9 GPIO_ACTIVE_HIGH>;
+ pinctrl-assert-gpios = <&lsio_gpio4 10 GPIO_ACTIVE_HIGH>;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ pm-ignore-notify;
+ keep-power-in-suspend;
+ non-removable;
+ cap-power-off-card;
+ status = "okay";
+};
+
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -1540,7 +1559,6 @@
fsl,pins = <
IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021
IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021
- IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021
>;
};
@@ -1618,7 +1636,26 @@
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
- IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc3_gpio: usdhc3grpgpio {
+ fsl,pins = <
+ IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 0x00000021
+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021
+ IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
>;
};
@@ -1680,13 +1717,11 @@
pinctrl_wlreg_on: wlregongrp{
fsl,pins = <
- IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000
>;
};
pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
fsl,pins = <
- IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000
>;
};