why there is a large gap among DMA transfers (LPSPI)

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why there is a large gap among DMA transfers (LPSPI)

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david_geng
Contributor I

Hi, 

I'm testing the maximum speed of the LPSPI port on a RT1021 board. I downloaded the official cmsis_lpspi_edma_b2b_transfer_master example and only changed the port to LPSPI3 and SPI clock to 50MHz. I just get 25MHz actually, but that's ok.

However, one thing slows the transfer down is that there appears to be a rather large gap (about 1us) among each transfer. So why is that during a DMA process? any chance to remove such limitation? 

Many thanks,

David

PS. enclosed the waveform captured

lpspi_wave.png

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david_geng
Contributor I

I think I mostly solved the problem. sorry for the false alarm.

The delay definitions in the RTE_Device.h need to be set to 0s for the fastest throughput. However, still there is a 120ns gap, I can understand that the LPSPI needs a few cycles to load the register or the DMA needs time to fetch the data. 

But interestingly there is no such gap between the first transfer and the second transfer. The waveform enclosed.

Cheers,lpspi_wave2.png

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Hui_Ma
NXP TechSupport
NXP TechSupport

Thanks for your feedback.

best regards,

Mike

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