iMXRT1052 and emwin planning SDRAM region with D Cache

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iMXRT1052 and emwin planning SDRAM region with D Cache

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Contributor III

Hi, 

I build a GUI using the emwin on the iMXRT1052, the lcd and gui buffer be placed in a cacheable region of planned SDRAM space. Actual operation result, it’s performance drop during moving actions of the GUI elements. I tried to enable the D-cache for the whole SDRAM, it’s OK.  But I can’t set the whole SDRAM to CACHE, the program needs to be placed Global data placement with SDRAM, and the region set to Non-cache, Is there any other solution?

The following is memory of the system configuration.

iMX RT1050 Memory setting:

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  • BOARD_SDRAM: Global data region.
  • BOARD_SDRAM_CACHE: Gui framebuffer used.
  • BOARD_SDRAM_NON_CACHE: Reserved.

iMX RT1050 Cache setting:

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GUI framebuffer mapping memory space:

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Best Regards,

Jim

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3 Replies

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NXP TechSupport
NXP TechSupport

Hello ,

Hope you are doing well.

I believe there are some important considerations to take mentioned in the following post: 

iMXRT1052 and emWin: problems with D cache 

The situation is similar and may help as well. Please let me know if its answers your questions regarding what should be cached and what shouldn't.

Let me know if you have further questions.

Best Regards,

Sabina

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Contributor III

Hi Sabina

I tried this web link about these problem, but it's situation is different from mine, it enable the D cache for the whole SDRAM , but I divide SDRAM into tree pieces, and first pieces of SDRAM set global data placement and non-cacheable region, second pieces of SDRAM set cacheable region to provide the LCD and GUI buffers access, but this setting will cause system performance drop during moving actions of the GUI elements.

pastedImage_24.png

pastedImage_5.png

Best Regards,

Jim

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57 Views
NXP TechSupport
NXP TechSupport

Hope you are doing well.

If you divide the three sections and place non-cacheable region, it can avoid the cache data coherency problem. But the side-effect is the performance of accessing the buffer is not good as cacheable ones if CPU access them multiple times. So it is expected that the performance drops. 

Maybe I misunderstood your questions, but could you please describe what is the main objective that you would like to achieve with these regions.

Best Regards,

Sabina

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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