iMXRT1021 - quad flexspi configuration with NOR flash.

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iMXRT1021 - quad flexspi configuration with NOR flash.

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Contributor III

Hi,

Our design uses the iMXRT1021 with a 32Mbit MX25L3233F qspi nor flash.

We would like to try re-configuring some of the qspi pin/bus parameters after POR. This would allow us to fine tune the qspi pin characteristics and hopefully optimise for EMC test performance.

The question is; is it possible and safe to do this and if so, how?

The NXP driver software has examples of gpio settings for various devices , but we are unable to find a setup for the flexspi bus pins.

Please advise on the best way to proceed.

br,

Tony

1 Solution
4 Views
NXP TechSupport
NXP TechSupport

Hi Tony

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Is it possible and safe to do this and if so, how?
-- Yes, it's available to do that, and I'd like to recommend run the codes in the internal RAM to make it.
In the flexspi_nor_polling_transfer in the SDK library, it contains the FlexSPI pins initialiation codes, you can refer to for details.

Have a great day,
TIC

 

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Contributor III

Hi Tony,

you can also check the flash configuration in the boot hdr:

to be found in evkmimxrt1020_flexspi_nor_config.c (xip folder).

This configuration is applied automatically when booting from flash.

For pin settings i created these defines:

/*----------------- Pin Configuration Defines -------------------------*/

// Hysteresis Enable Field
#define HYS_0_Hysteresis_Disabled (0 << 16)
#define HYS_1_Hysteresis_Enabled (1 << 16)

// Pull Up / Down Config Field
#define PUS_0_100K_Ohm_Pull_Down (0 << 14)
#define PUS_1_47K_Ohm_Pull_Up (1 << 14)
#define PUS_2_100K_Ohm_Pull_Up (2 << 14)
#define PUS_3_22K_Ohm_Pull_Up (3 << 14)

// Pull / Keep Select Field
#define PUE_1_Keeper (0 << 13)
#define PUE_1_Pull (1 << 13)

// Pull / Keep Enable Field
#define PKE_0_Pull_Keeper_Disabled (0 << 12)
#define PKE_1_Pull_Keeper_Enabled (1 << 12)

// Open Drain Enable Field
#define ODE_0_Open_Drain_Disabled (0 << 11)
#define ODE_1_Open_Drain_Enabled (1 << 11)

// Speed Field
#define SPEED_0_low_50MHz (0 << 6)
#define SPEED_1_medium_100MHz (1 << 6)
#define SPEED_2_medium_100MHz (2 << 6)
#define SPEED_3_max_200MHz (3 << 6)

// Drive Strength Field
#define DSE_0_output_driver_disabled (0 << 3)
#define DSE_1_R0_1_150_Ohm_3_3V_260_Ohm_1_8_V (1 << 3)
#define DSE_2_R0_2 (2 << 3)
#define DSE_3_R0_3 (3 << 3)
#define DSE_4_R0_4 (4 << 3)
#define DSE_5_R0_5 (5 << 3)
#define DSE_6_R0_6 (6 << 3)
#define DSE_7_R0_7 (7 << 3)

// Slew Rate Field
#define SRE_0_Slow_Slew_Rate (0)
#define SRE_1_Fast_Slew_Rate (1)

IOMUXC_SetPinMux( IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinConfig( IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B,

HYS_0_Hysteresis_Disabled |
PUS_0_100K_Ohm_Pull_Down |
PKE_1_Pull_Keeper_Enabled |
PUE_1_Pull |
ODE_0_Open_Drain_Disabled |
SPEED_0_low_50MHz |
DSE_0_output_driver_disabled |
SRE_0_Slow_Slew_Rate
);

Kind regards,

Johann

4 Views
Contributor III

Hi Johann,

Thank you for your input. That looks very comprehensive and useful.

br,

Tony

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5 Views
NXP TechSupport
NXP TechSupport

Hi Tony

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Is it possible and safe to do this and if so, how?
-- Yes, it's available to do that, and I'd like to recommend run the codes in the internal RAM to make it.
In the flexspi_nor_polling_transfer in the SDK library, it contains the FlexSPI pins initialiation codes, you can refer to for details.

Have a great day,
TIC

 

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

View solution in original post

4 Views
Contributor III

Hi Jeremy,

Thank you for the quick response.

We will look into the SDK for examples.

br,

Tony

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