iMXRT 1050-EVKB Memory Configuration Problems and Unclarities

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iMXRT 1050-EVKB Memory Configuration Problems and Unclarities

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tinraic_pionierkraft
Contributor I

Hello everybody,

I have a question regarding the memory configuration of the iMXRT 1052 microcontroller on the iMXRT 1050-EVKB evaluation board.

I'm running the Google IoT Hello Example with ethernet and LPSPI.

I use the internal 512 kB of SDRAM shared with TCM.

The RAM memory configuration and consumption is as shown in the picture:

Memory Configuration and ConsumptionMemory Configuration and Consumption

Any changes that I make to the configuration (ex. increase DTC, decrease ITC, remove OC...) cause the hard fault with the following details:

break at address "0x201434" with no debug information available, or outside of program code

Active faults
Bus Fault (BFSR)
IMPRECISERR (2) Imprecise data bus error
Hard Fault (HFSR)
FORCED (30) Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled

Fault Status Registers
IPSR 0x00000003 Exception Status Register (Hard Fault)
CFSR 0x00000400 Configurable fault Status Register
MMSR 0x00000000 Memory Manage fault Status Register
BFSR 0x00000004 Bus fault Status Register
UFSR 0x00000000 User fault Status Register
HFSR 0x40000000 Hard fault Status Register
DFSR 0x00000000 Debug fault Status Register
MMAR 0x00000000 Memory Manage fault Address Register
BFAR 0x00000000 Bus fault Address Register
ABFSR 0x00000002 Auxiliary Bus Fault Status Register

Stacked Registers (MSP LR/EXC_RETURN=0xfffffff9)
R0 0x00000000
R1 0x00000000
R2 0x00000000
R3 0x00000000
R12 0x00000000
LR 0x00000000
PC 0x00000000
PSR 0x00000000
MSP 0x2003FFD8

Some notes:

  • I have made myself familiar with the TCM on ARM-Cortex M processors, there is nowhere a requirement on the sizes or the number of the TCM regions
  • Including, removing, or reconfiguring the MPU has no effect on the outcome
  • The size of the RAM regions in every tried configuration always amount to 512 kB
  • All the sizes and start addresses of all of the tried configurations are in compliance with the memory layout in the reference manual

During the linking and flashing process (unsuccessful ones after the hard fault and flash corruption apparently caused by the wrong memory configuration), I have noticed the printout of the RT1050_connect.scp script:

============= SCRIPT: RT1050_connect.scp =============
RT1050 Connect Script
Error: Wire Ack Fault - target connected?
Error: Wire not connected
Error: Wire not connected
Disabling MPU
Error: Wire not connected
Error: Wire not connected
Configure FlexRAM for 256KB OC RAM, 128KB I-TCM, 128KB D-TCM
Error: Wire not connected
Error: Wire not connected
Error: Wire not connected
Finished
============= END SCRIPT =============================

So, it seems to me that the split of the internal RAM in the DTC, ITC, and OC region can't be (at least trivially) changed and reconfigured, but I can't find that explicitly written anywhere.

Is it really like that or have I overseen some deeper configuration requirements?

Thanks for the help.

Best regards,

Tin

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi tinraic_pionierkraft,

  Please check the AN12077, you will find that the ITCM, DTCM, OCRAM share 512KB flash.   

  If you want to change the related memory, you need to change the related register.

  In default, the OCRAM is 256KB, DTCM, and ITCM is 128KB.

  So, if you want to change the memory splite, you also need to modify the related memory register and code:

https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Reallocating-the-FlexRAM/ta-p/1117649

  You also need to modify the script file.

   You also can refer to this post, which will be useful to you:

https://community.nxp.com/t5/i-MX-RT/FlexRAM-and-Linker-Problem/m-p/990512

  Please try it on your side.

 BTW, please note, not all the item in the list can be modified:

image.png

 The Arm Cortex-M7 specifications require the size of ITCM/DTCM to be a power-of-two number, which can conflict with the FlexRAM configuration capability.

More details, please check the AN12077:

https://www.nxp.com/docs/en/application-note/AN12077.pdf

 

Wish it helps you!

If you still have questions about it, please kindly let me know.

Best Regards,

kerry

 

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