iMX RT1024 Hardware Design

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iMX RT1024 Hardware Design

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VarunKoganti
Contributor I

Hi,

I am trying to design a custom board using iMXRT1024.

I am using a DCDC converter (TPS54495RSAT‎) to power the board.

My design is such that when power is supplied to DCDC converter the board must power up.

How to connect the ONOFF, POR_B, WAKEUP, PMIC_ON_REQ & PNIC_STBY_REQ, USB_OTG1_CHD_B Pins?

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Kazillos
Contributor I

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Yuri
NXP TechSupport
NXP TechSupport

@VarunKoganti 
Hello,

 

  As I understand, internal i.MX DCDC is not used in Your design.
We do not have reference design for such configuration, nevertheless
below are some comments.

Use Figure 2 (Power control diagram) of Hardware Development Guide
for the MIMXRT1020 as base for design, assuming, that internal DCDC
for Your case should be disabled.

https://www.nxp.com/webapp/Download?colCode=MIMXRT1020HDUG

DCDC_PSWITCH should be connected to the ground to bypass DCDC.
(To enable DCDC function, assert to DCDC_IN with at least 1ms delay
for DCDC_IN rising edge.)

Please pay attention on Power Up Sequence Requirements, provided
in the Hardware Development Guide and the Datasheet(s).

 https://www.nxp.com/docs/en/data-sheet/IMXRT1024CEC.pdf

 https://www.nxp.com/docs/en/data-sheet/IMXRT1024IEC.pdf


PMIC_REQ_ON is used to enable the external DC/DC to power up other
power domains, assuming first, it powers up SNVS. Also, the ON/OFF
button is used to switch PMIC_REQ_ON on/off to control power modes;
the RESET button and the WDOG output are used to reset the system power.
Please refer to design recommendations in Hardware Development Guide
and use the reference schematic how to treat with other signals.

 https://www.nxp.com/webapp/Download?colCode=MIMXRT1024-EVK-Design-Files

 

Regards,
Yuri.

 

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VarunKoganti
Contributor I

@Yuri 

My design utilizes an external DCDC converter to generate +3v3 for VDD_SNVS_IN & VDD_HIGH_IN.

to supply the +1v1 for VDD_SOC_IN i will use internal DCDC converter.

the DCDC_PSWITCH is delayed usign RC circuit (30k ohm & 220nF) & DCDC_IN_Q is connected to 220nF capacitor from +3v3.

as said earlier I am stuck with POR_B, ONOFF, WAKEUP, PMIC_STDBY_REQ, PMIC_ON_REQ & USB_OTG1_CHD_B.

 

Can the POR_B connected to RC circuit or 55 timer in one shot mode to delay the RST?

Can PMIC_STBY_REQ, PMIC_ON_REQ be float as they will not control external DCDC converter? external DCDC converter will be enabled as PWR is connected to the circuit.

What is the use of this pin USB_OTG1_CHD_B?

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Yuri
NXP TechSupport
NXP TechSupport

@VarunKoganti 
Hello,

  You may follow NXP reference design and the Hardware Development Guide.
The POR_B input (if used) must be immediately asserted at power-up and
remain asserted until after the last power rail reaches its working
voltage. So, an external supervisor here is more preferable (than
just an RC circuit).
PMIC_STDBY_REQ may be left floating, if an external PMIC is not used.

PMIC_ON_REQ helps to meet power up sequence requirements. VDD_SNVS_IN
supply must be turned on first, after that, i.MX PMIC_ON_REQ is asserted
automatically in order to continue power up sequence for the rest voltages.

USB_OTG1_CHD_B is applied for USB charger detection.


https://community.nxp.com/t5/i-MX-RT/i-MX-RT1064-USB-OTG1-CHD-B/m-p/1302291

 

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