i.MX RT106x SEMC address alignment for external SRAM

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i.MX RT106x SEMC address alignment for external SRAM

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nickwallis
Senior Contributor I

Hello,

We are using MIMXRT1062DVJ6A with external SRAM memory (Cypress # CY7C1051DV33-10ZSXI), this memory is 512k x 16, we have two of them (on different chip selects), the external databus is x16. The SEMC is in ADMUX mode.

Does anybody know the address alignment when using the SEMC in this mode? I think it is x16 aligned, and so A1 from the MCU goes to A0 on the SRAM, etc..... (A0 from the MCU is not used).

Does anybody know for sure? The reference manual does not have much information on this.

thanks and regards

Nick Wallis

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jeremyzhou
NXP Employee
NXP Employee

Hi Nick Wallis,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Please connect the A0~A18 pin of CY7C1051DV33-10ZSXI to A0~A18 pins of i.MX RT1060.
Hope this is clear.

Have a great day,
TIC

 

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george
Senior Contributor II

Dear @jeremyzhou,

We are facing the same problem with the RT117x.

Do you think the answer given above also applies to RT117x?
*Does it apply to all RT series with SEMC?

BR,
George

1,036 Views
jeremyzhou
NXP Employee
NXP Employee

Hi @george 

1) Does it apply to all RT series with SEMC?

-- Yes.

BR,

Jeremy

1,032 Views
george
Senior Contributor II

Hello @jeremyzhou,

Thank you for your quick response.

As nickwallis says, this information doesn't seem to be included in the documentation provided by NXP.
Please ask the documentation team to add this content.

BR,
George