i.MX RT1064 LPSPI Boot - NOR Flash Command Set

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i.MX RT1064 LPSPI Boot - NOR Flash Command Set

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steve_n
Contributor II

Hello,

I'm looking into the LPSPI Serial NOR recovery boot option, described by section 9.6.5 Serial NOR/EEPROM through LPSPI of the IMXRT1064 Reference Manual.

We are planning on using a Cypress S25FL512S. 

I understand that the SCK, SDO, SDI, and CS is defined by the LPSPI_PORT_SEL number in Table 9-1. I also see LPSPI_ADDR and LPSIP_SPEED. What I don't see, is how does the MCU's boot ROM know the command set of the flash chip? How does it know what instruction to pass into the flash chip to read the initial 4KB to get the IVT, DCD table and so on?

Thank you.

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victorjimenez
NXP TechSupport
NXP TechSupport

Hi Steve, 

The recovery method mainly uses EEPROM memories which are a 1-bit read/normal read mode SPI interface. The select EEPROM needs to meet the EEPROM instructions standard.  It also supports Serial NOR flash, but if you use this type of memory, you need to verify that complies with the EEPROM standard.

The ROM bootloader knows how to communicate with this memory because it uses the EEPROM instructions standard, hence the instruction will always be the same. 

Note1: BootROM uses SPI Mode(0,0)CPOL=0, CPHA=0access type. You cannot modify this. 

Note2: BootROM mainly supports 2bytesstorage size is 4Kb - 512Kb / 3bytes1Mb - 128Mbaddress EEPROM/NOR.

One of my coworkers has made some tests with different memories to verify the recovery mode. The memories he used and worked fine are the followings: 

  • Onsemi CAT25512HU5I-GT3 (EEPROM, 1-bit SPI, 20MHz, 128B Page/512Kb Device)
  • Micron MT25QL128ABA1ESE-OSIT (NOR Flash, Multiple I/O, 133MHz-STR, 64B Page/4-32-64KB Sector/128Mb Device)
  • Spansion S25FL129P (NOR Flash, Multiple I/O, 80MHz, 256B Page/4-8-64-256KB Sector/128Mb Device)

These memories are just examples. As long as you choose a memory that complies with the information mentioned above you shouldn't have any problems. 

The coworker that made these tests also has a personal blog. Here he created a document regarding the EEPROM standard. Although the document is in Chinese, you can use the built-in translation of your browser to get the main idea of the blog. 

痞子衡嵌入式:串行EEPROM接口事实标准及SPI EEPROM简介 - 痞子衡 - 博客园 (cnblogs.com)

Regards,
Victor 

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steve_n
Contributor II

Great. Thanks.

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1,227 Views
victorjimenez
NXP TechSupport
NXP TechSupport

Hi Steve, 

The recovery method mainly uses EEPROM memories which are a 1-bit read/normal read mode SPI interface. The select EEPROM needs to meet the EEPROM instructions standard.  It also supports Serial NOR flash, but if you use this type of memory, you need to verify that complies with the EEPROM standard.

The ROM bootloader knows how to communicate with this memory because it uses the EEPROM instructions standard, hence the instruction will always be the same. 

Note1: BootROM uses SPI Mode(0,0)CPOL=0, CPHA=0access type. You cannot modify this. 

Note2: BootROM mainly supports 2bytesstorage size is 4Kb - 512Kb / 3bytes1Mb - 128Mbaddress EEPROM/NOR.

One of my coworkers has made some tests with different memories to verify the recovery mode. The memories he used and worked fine are the followings: 

  • Onsemi CAT25512HU5I-GT3 (EEPROM, 1-bit SPI, 20MHz, 128B Page/512Kb Device)
  • Micron MT25QL128ABA1ESE-OSIT (NOR Flash, Multiple I/O, 133MHz-STR, 64B Page/4-32-64KB Sector/128Mb Device)
  • Spansion S25FL129P (NOR Flash, Multiple I/O, 80MHz, 256B Page/4-8-64-256KB Sector/128Mb Device)

These memories are just examples. As long as you choose a memory that complies with the information mentioned above you shouldn't have any problems. 

The coworker that made these tests also has a personal blog. Here he created a document regarding the EEPROM standard. Although the document is in Chinese, you can use the built-in translation of your browser to get the main idea of the blog. 

痞子衡嵌入式:串行EEPROM接口事实标准及SPI EEPROM简介 - 痞子衡 - 博客园 (cnblogs.com)

Regards,
Victor 

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1,216 Views
steve_n
Contributor II

The ROM bootloader knows how to communicate with this memory because it uses the EEPROM instructions standard, hence the instruction will always be the same. 

Thank you for the information. This is what I what was looking for.

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victorjimenez
NXP TechSupport
NXP TechSupport

Hello Steve,

I'm checking this internally. I will provide you an update as soon as possible. 

Regards,
Victor 

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