My project requires a high bandwidth interconnection to an FPGA. I am going to use the SEMC in SRAM mode to implement it. Specifically, the SEMC would be used in ADMUX ( multiplexed address and data ), SYNC mode for both reads and writes. Figures 24-63 and 24-66 in the reference manual shows bus signals for these cases.
What is not clear in the reference manual are the SEMC pin assignments for the chip select and clock. Section 24.5.3 has a pin mux table for the SEMC with a column for SRAM.
That table lists CS6 on SEMC_ADDR, which according to table 9-1 is presented at GPIO_EMC_17. That seems straightforward enough. Is this correct ? Is only one chip select ( CS6 ) possible for SRAM mode ?
Next up is the clock. Table 9-1 lists SEMC_CLK on GPIO_EMC_26, but table 24-5-3 calls for SEMC_CLKX or SEMC_CLKX. Is GPIO_EMC_26 the physical pin where these clocks will be presented ?
Finally, the SEMC Pin Mux table 24-5-3 lists a signal named CRE appearing on SEMC_ADDR. What is this signal ?
There are some discrepancies in our i.MX RT1060 ReferenceManual:
the signals SEMC_CLKX and SEMC_CLKX also are named SEMC_CLK5
GPIO_SD_B0_02 has SEMC_CLK5 multiplexing option.
GPIO_SD_B0_0 has SEMC_CLK6 multiplexing option.