i.MX RT1050 with external 16-bit SDRAM and 16-bit SRAM

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i.MX RT1050 with external 16-bit SDRAM and 16-bit SRAM

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vonp
Contributor II

I am trying to configure the RT1050 to use the SEMC to interface to external 16-bit SDRAM and 16-bit SRAM(for fpga communication). I can get them to work independently, but when I combine them I get hardfault_handler.I am confused on CS and CE pin mux, as it seems that which ever one is declared first, will work. I have tried initializing the SRAM CE with kSEMC_MUXCSX2 and address of 0x8800001c and address 0x98000018 but always ends with hardfault. Am I correct in thinking that these can be used at the same time? Thanks in advance!

Using the following:

-IAR

-SDK_2.3.0_EVK-MIMXRT1050

-SDRAM init attached

-SEMC config

   /* Configure SDRAM. */
   sdramconfig.csxPinMux = kSEMC_MUXCSX0; //CS0
   sdramconfig.address = 0x80000000;
   sdramconfig.memsize_kbytes = 32 * 1024;//32 * 1024; /* 32MB = 32*1024*1KBytes*/
   sdramconfig.portSize = kSEMC_PortSize16Bit;
   sdramconfig.burstLen = kSEMC_Sdram_BurstLen4;//kSEMC_Sdram_BurstLen8;
   sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;
   sdramconfig.casLatency = kSEMC_LatencyTwo;
   sdramconfig.tPrecharge2Act_Ns = 21;//18; /* Trp 18ns */
   sdramconfig.tAct2ReadWrite_Ns = 21;//18; /* Trcd 18ns */
   sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
   sdramconfig.tWriteRecovery_Ns = 14; /* 12ns */
   sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);
   sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */
   sdramconfig.tSelfRefRecovery_Ns = 67;
   sdramconfig.tRefresh2Refresh_Ns = 60;
   sdramconfig.tAct2Act_Ns = 60;
   sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
   sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
   sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
   sdramconfig.refreshBurstLen = 1;
   return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);

   /* Configure ALTERA.*/
   altera_config.cePinMux = kSEMC_MUXCSX0;//CS2 PIN C7 SEMC_CSX0 added for altera
   altera_config.address = 0x8401001c;//added for altera
   altera_config.memsize_kbytes = 32 * 1024;//added for altera
   altera_config.portSize = kSEMC_PortSize16Bit;//added for altera
   altera_config.burstLen = kSEMC_Sdram_BurstLen2;//added for altera
   altera_config.addr27 = kSEMC_MORA27_NONE;//added for altera
   altera_config.tReLow_Ns = 18;//added for altera
   altera_config.readCycle = 10;//added for altera
   altera_config.addrMode = altera_config.addrMode | (0x03 << 8);//added for altera
   return SEMC_ConfigureSRAM(SEMC, &altera_config, clockFrq);//added for altera

-SDRAM initialization 

   void BOARD_SDRAM_Init()
   {
   // Config IOMUX for SDRAM
   writeRam(0x401F8014,0x00000000); // EMC_00
   writeRam(0x401F8018,0x00000000); // EMC_01
   writeRam(0x401F801C,0x00000000); // EMC_02
   writeRam(0x401F8020,0x00000000); // EMC_03
   writeRam(0x401F8024,0x00000000); // EMC_04
   writeRam(0x401F8028,0x00000000); // EMC_05
   writeRam(0x401F802C,0x00000000); // EMC_06
   writeRam(0x401F8030,0x00000000); // EMC_07
   writeRam(0x401F8034,0x00000000); // EMC_08
   writeRam(0x401F8038,0x00000000); // EMC_09
   writeRam(0x401F803C,0x00000000); // EMC_10
   writeRam(0x401F8040,0x00000000); // EMC_11
   writeRam(0x401F8044,0x00000000); // EMC_12
   writeRam(0x401F8048,0x00000000); // EMC_13
   writeRam(0x401F804C,0x00000000); // EMC_14
   writeRam(0x401F8050,0x00000000); // EMC_15
   writeRam(0x401F8054,0x00000000); // EMC_16
   writeRam(0x401F8058,0x00000000); // EMC_17
   writeRam(0x401F805C,0x00000000); // EMC_18
   writeRam(0x401F8060,0x00000000); // EMC_19
   writeRam(0x401F8064,0x00000000); // EMC_20
   writeRam(0x401F8068,0x00000000); // EMC_21
   writeRam(0x401F806C,0x00000000); // EMC_22
   writeRam(0x401F8070,0x00000000); // EMC_23
   writeRam(0x401F8074,0x00000000); // EMC_24
   writeRam(0x401F8078,0x00000000); // EMC_25
   writeRam(0x401F807C,0x00000000); // EMC_26
   writeRam(0x401F8080,0x00000000); // EMC_27
   writeRam(0x401F8084,0x00000000); // EMC_28
   writeRam(0x401F8088,0x00000000); // EMC_29
   writeRam(0x401F808C,0x00000000); // EMC_30
   writeRam(0x401F8090,0x00000000); // EMC_31   
   writeRam(0x401F8094,0x00000000); // EMC_32
   writeRam(0x401F8098,0x00000000); // EMC_33
   writeRam(0x401F809C,0x00000000); // EMC_34
   writeRam(0x401F80A0,0x00000000); // EMC_35
   writeRam(0x401F80A4,0x00000000); // EMC_36
   writeRam(0x401F80A8,0x00000000); // EMC_37
   writeRam(0x401F80AC,0x00000000); // EMC_38
   writeRam(0x401F80B0,0x00000010); // EMC_39, DQS PIN, enable SION
   writeRam(0x401F80B4,0x00000000); // EMC_40
   writeRam(0x401F80B8,0x00000000); // EMC_41   

   // PAD ctrl
   //   drive strength = 0x7 to increase drive strength
   // otherwise the data7 bit may fail.
   writeRam(0x401F8204,0x000110F9); // EMC_00
   writeRam(0x401F8208,0x000110F9); // EMC_01
   writeRam(0x401F820C,0x000110F9); // EMC_02
   writeRam(0x401F8210,0x000110F9); // EMC_03
   writeRam(0x401F8214,0x000110F9); // EMC_04
   writeRam(0x401F8218,0x000110F9); // EMC_05
   writeRam(0x401F821C,0x000110F9); // EMC_06
   writeRam(0x401F8220,0x000110F9); // EMC_07
   writeRam(0x401F8224,0x000110F9); // EMC_08
   writeRam(0x401F8228,0x000110F9); // EMC_09
   writeRam(0x401F822C,0x000110F9); // EMC_10
   writeRam(0x401F8230,0x000110F9); // EMC_11
   writeRam(0x401F8234,0x000110F9); // EMC_12
   writeRam(0x401F8238,0x000110F9); // EMC_13
   writeRam(0x401F823C,0x000110F9); // EMC_14
   writeRam(0x401F8240,0x000110F9); // EMC_15
   writeRam(0x401F8244,0x000110F9); // EMC_16
   writeRam(0x401F8248,0x000110F9); // EMC_17
   writeRam(0x401F824C,0x000110F9); // EMC_18
   writeRam(0x401F8250,0x000110F9); // EMC_19
   writeRam(0x401F8254,0x000110F9); // EMC_20
   writeRam(0x401F8258,0x000110F9); // EMC_21
   writeRam(0x401F825C,0x000110F9); // EMC_22
   writeRam(0x401F8260,0x000110F9); // EMC_23
   writeRam(0x401F8264,0x000110F9); // EMC_24
   writeRam(0x401F8268,0x000110F9); // EMC_25
   writeRam(0x401F826C,0x000110F9); // EMC_26
   writeRam(0x401F8270,0x000110F9); // EMC_27
   writeRam(0x401F8274,0x000110F9); // EMC_28
   writeRam(0x401F8278,0x000110F9); // EMC_29
   writeRam(0x401F827C,0x000110F9); // EMC_30
   writeRam(0x401F8280,0x000110F9); // EMC_31
   writeRam(0x401F8284,0x000110F9); // EMC_32
   writeRam(0x401F8288,0x000110F9); // EMC_33
   writeRam(0x401F828C,0x000110F9); // EMC_34
   writeRam(0x401F8290,0x000110F9); // EMC_35
   writeRam(0x401F8294,0x000110F9); // EMC_36
   writeRam(0x401F8298,0x000110F9); // EMC_37
   writeRam(0x401F829C,0x000110F9); // EMC_38
   writeRam(0x401F82A0,0x000110F9); // EMC_39
   writeRam(0x401F82A4,0x000110F9); // EMC_40
   writeRam(0x401F82A8,0x000110F9); // EMC_41

   //   Config SDR Controller Registers/
   writeRam(0x402F0000,0x10000004); // MCR
   writeRam(0x402F0008,0x00030524); // BMCR0
   writeRam(0x402F000C,0x06030524); // BMCR1
   writeRam(0x402F0010,0x80000017); //RLK1B); // BR0, 32MB
   writeRam(0x402F0014,0x8200001B); // BR1, 32MB
   writeRam(0x402F0018,0x8400001B); // BR2, 32MB
   writeRam(0x402F001C,0x8600001B); // BR3, 32MB
   writeRam(0x402F0020,0x90000021); // BR4,
   writeRam(0x402F0024,0xA0000019); // BR5,
   writeRam(0x402F0028,0xA8000017); // BR6,
   writeRam(0x402F002C,0xA900001B); // BR7,
   writeRam(0x402F0030,0x00000021); // BR8,
   writeRam(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE,    SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.   

   //writeRam(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
   writeRam(0x402F0040,0x00000F31); // SDRAMCR0
   writeRam(0x402F0044,0x00652922); // SDRAMCR1
   writeRam(0x402F0048,0x00010920); // SDRAMCR2
   writeRam(0x402F004C,0x50210A08); // SDRAMCR3

   writeRam(0x402F0080,0x00000021); // DBICR0
   writeRam(0x402F0084,0x00888888); // DBICR1
   writeRam(0x402F0094,0x00000002); // IPCR1
   writeRam(0x402F0098,0x00000000); // IPCR2

   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000C); // SD_CC_IAF
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000C); // SD_CC_IAF
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F00A0,0x00000033); // IPTXDAT
   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000A); // SD_CC_IMS
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.   

   }

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1 Solution
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vonp
Contributor II

Yuri,

Thanks for the response, I think I was able to get it working. When stepping through the code I found that the compiler was executing the init for the SDRAM and would skip over the SRAM init. I put the SRAM init in its own separate function and it seems to be working from what I have tested so far. Thanks again! 

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4 Replies
630 Views
hanan_hayot
Contributor I

in the pinmux ,are you setting two separate Sdram parts ? Can you share your pinmux file ?

Thanks 

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630 Views
vonp
Contributor II

Hanan,

Sorry for the late reply. I init one as sram and the other as sdram. 

Here is the pinmux:

//****************************************************************************
// BOARD_InitPinsSemc(void)
//****************************************************************************
void BOARD_InitPinsSemc(void) {

IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 is configured as SEMC_ADDR00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 is configured as SEMC_ADDR01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 is configured as SEMC_ADDR02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 is configured as SEMC_ADDR03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 is configured as SEMC_ADDR04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 is configured as SEMC_ADDR05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 is configured as SEMC_ADDR06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 is configured as SEMC_ADDR07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 is configured as SEMC_ADDR08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 is configured as SEMC_ADDR09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 is configured as SEMC_ADDR11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 is configured as SEMC_ADDR12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 is configured as SEMC_BA0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 is configured as SEMC_BA1 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 is configured as SEMC_ADDR10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 is configured as SEMC_CAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 is configured as SEMC_RAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 is configured as SEMC_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 is configured as SEMC_CKE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 is configured as SEMC_WE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 is configured as SEMC_CS0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 is configured as SEMC_DATA08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 is configured as SEMC_DATA09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 is configured as SEMC_DATA10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 is configured as SEMC_DATA11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 is configured as SEMC_DATA12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 is configured as SEMC_DATA13 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 is configured as SEMC_DATA14 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 is configured as SEMC_DATA15 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 is configured as SEMC_DM01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 is configured as SEMC_DQS */
1U); /* Software Input On Field: Force input path of pad GPIO_EMC_39 */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 is configured as SEMC_RDY */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 PAD functional properties : */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 PAD functional properties : */
0x0110F9u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 PAD functional properties : */
0x0110F9u);

IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 PAD functional properties : */
0x0110F9u);

}

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  Check  i.MX RT1050 SDRAM and SRAM connection, using pin multiplexing,

shown in section 49.4.3 (Pin Mux in SEMC) of the i.MX RT1050 Reference

Manual, Rev. 1, 03/2018.

Have a great day,

Yuri

 

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Note: If this post answers your question, please click the Correct Answer

button. Thank you!

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vonp
Contributor II

Yuri,

Thanks for the response, I think I was able to get it working. When stepping through the code I found that the compiler was executing the init for the SDRAM and would skip over the SRAM init. I put the SRAM init in its own separate function and it seems to be working from what I have tested so far. Thanks again! 

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