In page 11 of the i.MX RT1050 datasheet, UART module is summarized as having "Programmable baud rates up to 5 Mbps." With further research into the clock tree and reference manual, it seems that the baud rate could be as high as 20 Mbps as follows:
PLL3 (pll3_sw_clk) = 480 MHz / 6 = 80 MHz = UART_CLK_ROOT which feeds the BAUD Divider.
Baud rate = baud clock /( (OSR+1) x SBR)
Max. Baud Rate: OSR = 3 (4x Oversampling) and SBR = 1 => 80 MHz / ((3+1) x 1) = 20 Mbps
Is there something incorrect about the above calculation and assumptions or is the statement about 5 Mbps incorrect?
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Hi Aaron
I escalated internally your question and got below answer :
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Baudrate beyond DS is not guaranteed, though you can set it to be higher.
The data gave in DS is fully tested and simulated, and passed.
----------------
Best regards
igor
Hi Aaron
statement about 5 Mbps is correct and restriction is defined by pads and
internal module dleays, not just max. clock tree frequencies.
Best regards
igor
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Thanks for the response, igor. I assume you are deriving the 5mbps restriction from the pad specifications from section 4.3.2.1 which is referenced on page 72 for the LPUART timing. Would you mind explaining how that figure is derived from those specs?
Hi Aaron
I will recheck internally and update.
Best regards
igor
Hi Aaron
I escalated internally your question and got below answer :
---------------
Baudrate beyond DS is not guaranteed, though you can set it to be higher.
The data gave in DS is fully tested and simulated, and passed.
----------------
Best regards
igor