Hi, I have a couple of questions regarding power-up/power-down sequencing and the use of external DCDC converter.
1. The recommended power control scheme is this:
I can clearly see that this scheme satisfies the power-up sequence requirement which says SNVS_IN must be powered prior to all other modules. However, I failed to see how this will satisfy the power-down sequence requirement that says SNVS_IN supply must be turned off after any other supplies. When the 5V source supply is turned off everything will power down at virtually the same time, no?
2. I have seen some custom board designs, including some commercial ones) featuring i.MX RT chips that do not use any external DC/DC component, which means the power-up/power-down sequences are not being implemented, and yet these designs work, haven't seen them failed yet. Can NXP/anyone shed some light as to why these designs work? To see this is done for a commercial product seems to suggest that the designers must have a high level of confidence about this.
Ok, found the answer in this thread:
Though it continues to baffle me why the documentation went as far as stating the possibility of "irreversible damage to the processor" when in the end it's so casually mentioned that the external DC/DC circuitry is not absolutely needed.