Hi
We have a system set up with iMx CPUs running freeRTOS (there we have a 1ms and 5ms cyclic task).
We also run lwip stack. The fast realtime routine are running interrupt triggered (ADC conversion end irqs, prio 1 and 2 and PWM reload prio 3).
Just to be precise the ADC conversion is triggered by PWM reload/compare event.
Set interrupt priorities are these:
#define NVIC_PRI_RESET (-3) // Not configurable
#define NVIC_PRI_NMI (-2) // IRQ -14, Not configurable
#define NVIC_PRI_HARDFAULT (-1) // IRQ -13, Not configurable
#define NVIC_PRI_ADC1 (1U) // IRQ 119 ADC1 complete (main pwm start), highest fast prio
#define NVIC_PRI_ADC0 (2U) // IRQ 118 ADC0 complete
#define NVIC_PRI_WAV (3U) // IRQ 102, Pattern generator, lowest fast priority
#define NVIC_PRI_DISABLE_ALL_BUT_FAST (7U) // Warning: Same as configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY in FreeRTOSConfig.h
// Value for basepri to disable all interrupts except the motor control ones.
// Don't call rtos functions from higher priorities, (-3 to 3).
#define NVIC_PRI_SDCARD (8U) // IRQ 110, USHDC1 for SD Card
#define NVIC_PRI_LPUART (8U) // IRQ 20, LPUART for serail port
#define NVIC_PRI_LPSPI (8U) // IRQ 33, LPSPI2 for serial flash
#define NVIC_PRI_SD_CD (9U) // IRQ 85, GPIO3 inputs 16 - 31, SD card detect
#define NVIC_PRI_ETHERNET (9U) // IRQ 114, Ethernet
#define NVIC_PRI_PENDSV (15U) // IRQ -2, Request for priviliged access
#define NVIC_PRI_SYSTICK NVIC_PRI_PENDSV // IRQ -1, RTOS tick
In the code I meassure start (signal ... S) and end (siganl ... E) of the irqs by latching the PWM timer PWM1->SM[0].CNT
When having a look on those timer values I see significant jitter (glitches) on the timing - see picture attached (3500 is about 50us). HOW could it be improved (harder real time, less jitter).
Note: IRQ table is copied in fast (internal) RAM, all routine code running in the fast irqs is placed in internal RAM.
Regards
Thomas
