i.MX RT 1064 evk DTCM problem

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i.MX RT 1064 evk DTCM problem

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allen_tseng
Contributor I

Hi

When I build my project, then the DTCM is full.

So I refer the thread to change sram alignment.

 

FlexRAM and Linker Problem 

But when I using mcuxpresso debug tool, debug message is below.

-----------------------------------------------------------------------------------------------------------

Active faults
Bus Fault (BFSR)
IMPRECISERR (2) Imprecise data bus error
Hard Fault (HFSR)
FORCED (30) Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled

Fault Status Registers
IPSR 0x00000003 Exception Status Register (Hard Fault)
CFSR 0x00000400 Configurable fault Status Register
MMSR 0x00000000 Memory Manage fault Status Register
BFSR 0x00000004 Bus fault Status Register
UFSR 0x00000000 User fault Status Register
HFSR 0x40000000 Hard fault Status Register
DFSR 0x00000000 Debug fault Status Register
MMAR 0x00000000 Memory Manage fault Address Register
BFAR 0x00000000 Bus fault Address Register
ABFSR 0x00000002 Auxiliary Bus Fault Status Register

Stacked Registers (MSP LR/EXC_RETURN=0xfffffff9)
R0 0x00000000
R1 0x00000000
R2 0x00000000
R3 0x00000000
R12 0x00000000
LR 0x00000000
PC 0x00000000
PSR 0x00000000
MSP 0x2003FFD8

-----------------------------------------------------------------------------------------------------------

Is the step I configured wrong?

Or what should I configure?

Please help me to solve this problem.

Thank you

 

Allen

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269 Views
jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Allen,

Thanks for your reply.
1) How do I decide the variable put in which area?
-- In my experience, I usually consider three aspects to decide which RAM area to store the variables.
Firstly, the RAM should have enough space to store the variables, secondly, these variables whether will occupy the heap area, last, it's about the cache feature of the CM7, and you needn't consider it when using either DTCM or ITCM, you can learn the maintenance of cache via referring to the application note: https://www.nxp.com/docs/en/application-note/AN12042.pdf

Have a great day,
TIC

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allen_tseng
Contributor I

Hi jeremyzhou

Thanks for your reply.

It's very useful.

And I have one more question.

---Last, increase the Heap size and set Stack's location at the Start instead of End, and I'd like to suggest configure the NonCacheable area in other memory areas instead of SRAM_DTC.

Is this have document or example can let me refer?

And I saw this thread, if put some register in ocram will not trigger interrupt.

基于freertos在开发板RT1052上枚举USB设备时无法触发中断 

My question is how do I know the variable will put in which area(ITCM, DTCM, OCRAM)?

Or how do I decide the variable put in which area?

This is first that I use the chip.

If I have wrong, please correct me.

Thanks

 

Allen

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Allen,

Thanks for your reply.
1) How do I decide the variable put in which area?
-- In my experience, I usually consider three aspects to decide which RAM area to store the variables.
Firstly, the RAM should have enough space to store the variables, secondly, these variables whether will occupy the heap area, last, it's about the cache feature of the CM7, and you needn't consider it when using either DTCM or ITCM, you can learn the maintenance of cache via referring to the application note: https://www.nxp.com/docs/en/application-note/AN12042.pdf

Have a great day,
TIC

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- We are following threads for 7 weeks after the last post, later replies are ignored
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allen_tseng
Contributor I

Hi jeremyzhou

Thanks for your reply.

I want to know, how to let variable to different ram area.

For example, when .bss set to DTCM, but DTCM fulled.

How do I separate .bss to OCRAM. Like this

.bss -> DTCM

.bss -> OCRAM

When I declared variable ,can I assign it in DTCM or OCRAM?

 

Allen

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Allen,

Thanks for your reply.
1) When I declared variables, can I assign it in DTCM or OCRAM?
-- Yes, you can, the different IDEs provide the related way to do it, and you can learn it by referring to IDE's user guide.

Hope it helps.

Have a great day,
TIC

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allen_tseng
Contributor I

Hi jeremyzhou

Thanks for your reply

I found the method to assign variables to different bank in MCUXpresso IDE's user guide.

The syntax is below.

__DATA(RAM3) char data_buffer[10]={0,1,2,3,4,5,6,7,8,9};

And I modify the .scp file to use debug well.

Thanks for your help

Allen

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Firstly, please follow the article (https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Reallocating-the-FlexRAM/ta-p/1117649) to configure the FlexRAM memory assignment,
Secondly, when you debug the project, it should modify the SCP file to fit the reconfiguration of the FlexRAM memory, and I've attached an SCP file and you can refer to it for details.

Last, increase the Heap size and set Stack's location at the Start instead of End, and I'd like to suggest configure the NonCacheable area in other memory areas instead of SRAM_DTC.

jeremyzhou_0-1602130063307.png

 


Have a great day,
TIC

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