If I understand the documentation correctly the delay between fault input and switching off the PWM output is mentioned in this text:
The values of FILT_PER and FILT_CNT must also be traded off against the desire
for minimal latency in recognizing input transitions. Turning on the input filter
(setting FILT_PER to a non-zero value) introduces a latency of ((FILT_CNT+4) x
FILT_PER x IPBus clock period). Note that even when the filter is enabled, there is a
combinational path to disable the PWM outputs. This is to ensure rapid response to
fault conditions and also to ensure fault response if the PWM module loses its clock.
The latency induced by the filter will be seen in the time to set FSTS[FFLAG] and
So with FILT_CNT=0 (what I assume is the default) I should have a delay of 4 x
FILT_PER x IPBus clock period or is it zero for FILT_CNT=0?
Currently I measure a delay of about 1.5us between fault input (power stack interface signal) and IGBT driving signals (combinational path is off, prescaler shall be 2, pwmConfig.clockSource = kPWM_BusClock) what seems to be quite high.
Is there something I miss or must the delay then come from external components.
Hope you are well.
Could you please provide me the part number you are working with?
If FILT_CNT = 0 the approximated delay should be 4 x FILT_PER x IPBus clock period. Even with this it important to consider that fault starts considering the input after the third sample when FILT_CNT is 0.
If you have more questions do not hesitate to ask me.