connection problem with ENET2 on RT1061

[ThomasSC]

Hello,

I use the RT1061 with the 2nd network interface (ENET2). The Ethernet-Phy (a KSZ8863MLL) is connected via the MII interface.
Unfortunately, after power on a connection to the network is not always established.

With the DHCP demo, no send telegram (DHCP discover) can be seen in the error state on the network.
Are there any known problems with this configuration?

Regards

Thomas

[ThomasSC · Accepted solution]

Hello,

it always works now, with the internal 25 MHz and the MII-Phy at REF_CLK.
The solution was to additionally set the ENET2_CLK_SEL bit in IOMUX_GPR_GPR1.
Based on the description in the reference manual, this was not so obvious to me.
Many thanks for the support.

Regards

Thomas

[mjbcswitzerland]

Hi

Check the HW counters in the EMAC to see whether it is counting Tx, Rx or errors.

A typical configuration issue is with the clock directions - do you supply the PHY with the clock or does the phy deliver the clock (the setup must match)?

Both Ethernet interfaces (ENET1, ENET2 or ENET1 and ENET2) [as well as KSZ8863 with tail-tagging option to run each of its interfaces as isolated ports] are supported in the uTasker project on either a shared network or on two isolated networks (and more with tail-tagged option) and the various configurations have been verified in a number of industrial product developments. In addition it allows the two ENET interfaces (and the compete TCP/IP stack operation) to be emulated in Visual Studio to make debugging and development simpler.
https://www.utasker.com/iMX/RT1060.html

Regards

Mark

[ThomasSC]

Hello,
The clock is supplied by the RT1061 (pin ENET2_REF_CLK2, 25 MHz) and is also present in the error state.
Which HW counters do you mean?
The ENET2 IEEE_T-registers are all at 0.

Regards

Thomas

[mjbcswitzerland]

Hi

Those HW Tx counters (the ones you referred to) should be incrementing when frames are sent. If not it is likely that a clock is missing - check that the 25MHz signal is really being sent out and also that there is a loop-back set in the output pin's characteristics so that the ENET2 module also receives the clock it is being generating for the PHY.

I have attached the 1062 MII port configuration that I use for ENET2. It is not SDK compatible but is easier to read so can easily be used for comparing.

Regards

Mark

[ThomasSC]

Hello,

A problem I have found so far is that the KSZ8863 and the RT1061 have the TX_CLK set to output. The clock direction of the KSZ8863 seems to be fixed. If the TX_CLK is set to input on the RT1061, the REF_CLK must also be fed in. The KSZ8863 is currently supplied by the REF_CLK of the RT1061. In order to solve this, an additional external oscillator is required. Am I right with that?

Regards

Thomas

[mjbcswitzerland]

Hi

In RMII mode the i.MX RT can supplies a 50MHz reference clock to the KSZ8863's TXCLK and RXCLK inputs.

In MII mode the KSZ8863 TXCLK and RXCLK are outputs and the i.MX RT can supply its X1 input with a 25MHz clock (avoiding the need to use a crystal).

Regards

Mark