Why does the SDK's evkmimxrt1060_sdram_ini_dcd.c configure all of the SEMC regions?

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Why does the SDK's evkmimxrt1060_sdram_ini_dcd.c configure all of the SEMC regions?

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Senior Contributor II

I'm working on an SEMC NOR/SRAM issue, and started digging into the evkmimxrt1060_sdram_ini_dcd.c file from the SDK because it has to configure SEMC-SDRAM space.  It appears that all of the SEMC regions are configured and made valid, which I suppose if configured correctly there's no harm done; however, it configures the final NAND region (BR8) to start at location 0.

So two questions...

1. is there any reason why unused regions are marked "valid" in the SEMC space?

2. with BR8 being configured to 0, why doesn't that trigger some kind of conflict with ITCM?

Thanks,

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NXP TechSupport
NXP TechSupport

Hi EdSutter,

   Talk about my understanding about your confusing that :

*(uint32_t*)0x402F0020 = 0x90000021;

*(uint32_t*)0x402F0030 = 0x00000021;

The BR8 BA is 0 which let you think the base address is 0.

Please check the RM about the BR4 and BR8 at first:

image.pngimage.png

You can find the BR4 just support the AXI, it need to use the BA which is memory map to the RT chip as the address.

But the BR8 just support the IP command only, this means, you can't use the AXI method to memory map it to the RT internal memory address, you need to use the external NAND flash related address which is really based from 0 to the external nand flash, this address is not for the RT, it for the Nand flash.

So, I think this is the reason to configure it as 0, at last, this register still needs to use the IP commander code to community with the external nandflash.

Wish it helps you!

If you still have questions about it, please kindly let me know!

Best Regards,

Kerry

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        #define GROUP1_ENTRIES       117
        #define GROUP2_ENTRIES       2
        #define GROUP3_ENTRIES       2
        #define GROUP4_ENTRIES       3
        #define GROUP5_ENTRIES       1

        typedef struct _PACK stDCD_TABLE {
            DCD_HEADER    dcd_header;
            unsigned char dcd_command1[GROUP_SIZE(GROUP1_ENTRIES)];
            unsigned char dcd_wait1[DCD_WAIT_SIZE];
            unsigned char dcd_command2[GROUP_SIZE(GROUP2_ENTRIES)];
            unsigned char dcd_wait2[DCD_WAIT_SIZE];
            unsigned char dcd_command3[GROUP_SIZE(GROUP3_ENTRIES)];
            unsigned char dcd_wait3[DCD_WAIT_SIZE];
            unsigned char dcd_command4[GROUP_SIZE(GROUP4_ENTRIES)];
            unsigned char dcd_wait4[DCD_WAIT_SIZE];
            unsigned char dcd_command5[GROUP_SIZE(GROUP5_ENTRIES)];
        } DCD_TABLE;

        #if defined _COMPILE_IAR
        __root const DCD_TABLE __dcd_data @ ".boot_hdr.dcd_data" // __root forces the function to be linked in IAR project
        #elif defined _GNU
        static const DCD_TABLE __attribute__((section(".boot_hdr.dcd_data"))) __dcd_data
        #elif defined _COMPILE_KEIL
        __attribute__((section("_DCD_DATA"))) const DCD_TABLE __dcd_data
        #else
        static const DCD_TABLE __dcd_data                                        // IS42S16160J-6BLI SDRAM configuration
        #endif
        = {
            { DCD_TAG, {BIG_SHORT_WORD_BYTES(sizeof(DCD_TABLE))}, DCD_VERSION }, // header
            {   // Command group 1
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP1_ENTRIES),
                _DCD_WRITE_LONG_WORD(CCM_CCGR0, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR1, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR2, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR3, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR4, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR5, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR6, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_ANALOG_PLL_SYS, (CCM_ANALOG_PLL_SYS_ENABLE | CCM_ANALOG_PLL_SYS_DIV_SELECT)), // enable the system PLL (PLL2)
                _DCD_WRITE_LONG_WORD(CCM_ANALOG_PFD_528, (29 << 16)), // system PLL PFD2 fractional mask for 327.7241379MHz
              //_DCD_WRITE_LONG_WORD(CCM_ANALOG_PFD_528, (35 << 16)), // system PLL PFD2 fractional mask for 271.5428571MHz
                _DCD_WRITE_LONG_WORD(CCM_CBCDR, (CCM_CBCDR_SEMC_PODF_DIV2 | CCM_CBCDR_AHB_PODF_DIV4 | CCM_CBCDR_IPG_PODF_DIV2 | CCM_CBCDR_SEMC_CLK_SEL_SEMC | CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2_PFD2)), // select SEMC_CLK_ROOT from PLL2-PFD2 divided by 2 to give 163.86MHz (max. 166MHz)
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, GPIO_EMC_00_SEMC_DATA00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, GPIO_EMC_01_SEMC_DATA01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, GPIO_EMC_02_SEMC_DATA02),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, GPIO_EMC_03_SEMC_DATA03),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, GPIO_EMC_04_SEMC_DATA04),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, GPIO_EMC_05_SEMC_DATA05),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, GPIO_EMC_06_SEMC_DATA06),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, GPIO_EMC_07_SEMC_DATA07),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, GPIO_EMC_08_SEMC_DM00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, GPIO_EMC_09_SEMC_ADDR00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, GPIO_EMC_10_SEMC_ADDR01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, GPIO_EMC_11_SEMC_ADDR02),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, GPIO_EMC_12_SEMC_ADDR03),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, GPIO_EMC_13_SEMC_ADDR04),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, GPIO_EMC_14_SEMC_ADDR05),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, GPIO_EMC_15_SEMC_ADDR06),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, GPIO_EMC_16_SEMC_ADDR07),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, GPIO_EMC_17_SEMC_ADDR08),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, GPIO_EMC_18_SEMC_ADDR09),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, GPIO_EMC_19_SEMC_ADDR11),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, GPIO_EMC_20_SEMC_ADDR12),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, GPIO_EMC_21_SEMC_BA0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, GPIO_EMC_22_SEMC_BA1),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, GPIO_EMC_23_SEMC_ADDR10),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, GPIO_EMC_24_SEMC_CAS),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, GPIO_EMC_25_SEMC_RAS),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, GPIO_EMC_26_SEMC_CLK),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, GPIO_EMC_27_SEMC_CKE),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, GPIO_EMC_28_SEMC_WE),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, GPIO_EMC_29_SEMC_CS0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, GPIO_EMC_30_SEMC_DATA08),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, GPIO_EMC_31_SEMC_DATA09),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, GPIO_EMC_32_SEMC_DATA10),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, GPIO_EMC_33_SEMC_DATA11),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, GPIO_EMC_34_SEMC_DATA12),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, GPIO_EMC_35_SEMC_DATA13),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, GPIO_EMC_36_SEMC_DATA14),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, GPIO_EMC_37_SEMC_DATA15),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, GPIO_EMC_38_SEMC_DM01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, IOMUXC_SW_MUX_CTL_PAD_SION),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, GPIO_EMC_40_SEMC_RDY),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, GPIO_EMC_41_SEMC_CSX0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
    #if defined iMX_RT1062
        #if defined APPLICATION_REQUIRES_GPIO_EMC_39
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_BTO_DEFAULT)),  // dummy read strobe loopbacked internally reduces the maximum speed of operation
        #else
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_BTO_DEFAULT | SEMC_MCR_DQSMD)),
        #endif
    #else
        #if defined APPLICATION_REQUIRES_GPIO_EMC_39
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (0)),                     // dummy read strobe loopbacked internally reduces the maximum speed of operation
        #else
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_DQSMD)),        // DQS(read strobe) mode
        #endif
    #endif
                _DCD_WRITE_LONG_WORD(SEMC_BMCR0, 0x00030524),            // queue A weigth settings
                _DCD_WRITE_LONG_WORD(SEMC_BMCR1, 0x06030524),            // queue B weigth settings
                _DCD_WRITE_LONG_WORD(SEMC_BR0,  (SDRAM_ADDR | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 0
                _DCD_WRITE_LONG_WORD(SEMC_BR1,  ((SDRAM_ADDR + (32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 1
                _DCD_WRITE_LONG_WORD(SEMC_BR2,  ((SDRAM_ADDR + (2 * 32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 2
                _DCD_WRITE_LONG_WORD(SEMC_BR3,  ((SDRAM_ADDR + (3 * 32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 3
                _DCD_WRITE_LONG_WORD(SEMC_BR4,  ((SDRAM_ADDR + (256 * 1024 * 1024)) | SEMC_BR_MS_256MB | SEMC_BR_VLD)), // base 4
                _DCD_WRITE_LONG_WORD(SEMC_BR5,  ((SDRAM_ADDR + (2 * 256 * 1024 * 1024)) | SEMC_BR_MS_16MB | SEMC_BR_VLD)), // base 5
                _DCD_WRITE_LONG_WORD(SEMC_BR6,  ((SDRAM_ADDR + (((2 * 256) + 132) * 1024 * 1024)) | SEMC_BR_MS_8MB | SEMC_BR_VLD)), // base 6
                _DCD_WRITE_LONG_WORD(SEMC_BR7,  ((SDRAM_ADDR + (((2 * 256) + 132 + 16) * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 7
                _DCD_WRITE_LONG_WORD(SEMC_BR8,  (0 | SEMC_BR_MS_256MB | SEMC_BR_VLD)), // base 8
                _DCD_WRITE_LONG_WORD(SEMC_IOCR, (SEMC_IOCR_MUX_RDY_NAND_RDY_WAIT |SEMC_IOCR_MUX_CSX3_DBI_CSX | SEMC_IOCR_MUX_CSX2_NAND_CE | SEMC_IOCR_MUX_CSX1_PSRAM_CE | SEMC_IOCR_MUX_CSX0_NOR_CE | SEMC_IOCR_MUX_A8_SDRAM_A8)),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR0, 0x00000f31),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR1, 0x00652922),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR2, 0x00010920),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR3, 0x50210a08),
                _DCD_WRITE_LONG_WORD(SEMC_DBICR0, 0x00000021),
                _DCD_WRITE_LONG_WORD(SEMC_DBICR1, 0x00888888),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR1, 0x00000002),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR2, 0x00000000),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, 0x80000000),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_PRECHARGE_ALL)),
            },
            {   // Wait 1
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 2
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP2_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH)),
            },
            {   // Wait 2
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 3
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP3_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH)),
            },
            {   // Wait 3
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 4
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP4_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPTXDAT, (0x00000033)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_MODESET)),
            },
            {   // Wait 4
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 5
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP5_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR3, (0x50210a08 | SEMC_SDRAMCR3_REN)),
            },
        };
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Senior Contributor II

Hey Mark,

Yea, I see what you're doing, but I ultimately need SDRAM, NOR and PSRAM to be configured (see this post), that's why I'm digging into this a bit more than I care to (i.e. it doesn't work for me, and I'm hoping its because I just don't understand something).

I started with the DCD file from the SDK, and that's where my confusion starts... First of all, it enables  (sets the valid bit) all of the devices within SEMC space, but on top of that the final base register appears to be mapped to address zero (unless I am totally misunderstanding how to configure SEMC space).  So it seems to me that this is fundamentally wrong because it overlaps with ITCM.

See my confusion?  You're more than welcome to call me an idiot and tell me what I'm doing wrong; especially if it gets me over my current "SEMC->NOR" hardfault! 

Ed 

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Specialist V

Hi Ed

I see that in my previous post the code is still there but all the text has gone missing - did you see/read the text at some point? I think it was OK when I posted back then but must it have lost the rest at some point.

I also don't remember exactly what I wrote but do remember that the idea was to show that the table can be made much more readable and that the entry

_DCD_WRITE_LONG_WORD(SEMC_BR8,  (0 | SEMC_BR_MS_256MB | SEMC_BR_VLD)), // base 8

is probably the one that you are referring to since it is (more understandably) configuring the 8th base to 0x00000000 and setting it as valid. This also makes it easier for NXP support to understand exactly what you are referring to.

 

Did you try simply removing the valid bit since then it would not be able to affect anything?

Regards

Mark

 

 

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Senior Contributor II

Hey Mark,

No, I never saw any text in your previous last post.

Yes, that is the primary line that has me confused (although, since the point of the file is to configure SDRAM, I don't understand why ANY of the other regions were enabled).  I did remove them in my own stuff; but I was trying to understand...

1) why they were even there

2) why didn't BR8 mapped to 0 cause some kind of exception because it collides with ITCM at 0x0.

 

The original SEMC problem we were having (writing to SEMC->NOR space) has been somewhat resolved.  I now use IPCMD for those transactions, but there are still timing issues (see my current state here  if interested).

Thanks,

Ed

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Specialist V

Hi Ed

I "suspect" that there is essentially one DCD reference used for all memory types.
And, maybe, there is a form of priority which means that ITC does not get affected when the address range overlaps.

Disabling the ranges that are not needed is probably the best thing to do (which will also avoid uncomfortable questions from ever being raised in code review meetings).

Regards

Mark

 

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Senior Contributor II

Yep, I agree with your suspicions; but I was hoping for some official answers.

I went down this rabbit hole because of the other SEMC issue I was having, it wasn't just a curious adventure I can assure you! 

Tx

Ed

 

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NXP TechSupport
NXP TechSupport

Hi EdSutter,

   Talk about my understanding about your confusing that :

*(uint32_t*)0x402F0020 = 0x90000021;

*(uint32_t*)0x402F0030 = 0x00000021;

The BR8 BA is 0 which let you think the base address is 0.

Please check the RM about the BR4 and BR8 at first:

image.pngimage.png

You can find the BR4 just support the AXI, it need to use the BA which is memory map to the RT chip as the address.

But the BR8 just support the IP command only, this means, you can't use the AXI method to memory map it to the RT internal memory address, you need to use the external NAND flash related address which is really based from 0 to the external nand flash, this address is not for the RT, it for the Nand flash.

So, I think this is the reason to configure it as 0, at last, this register still needs to use the IP commander code to community with the external nandflash.

Wish it helps you!

If you still have questions about it, please kindly let me know!

Best Regards,

Kerry

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View solution in original post

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Senior Contributor II

Kerry,

Thanks for the reply...

I have to admit that I don't have a strong grasp on IP / AXI inner workings here, but I see (as you point out) your point about BR8.  I suppose that explains why there is no clash with ITCM (assuming 0 is considered the base address of the NAND).   Hopefully you can agree that the documentation really needs to be updated for this to be understood without support.

Again, thanks for the explanation.

Ed

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NXP TechSupport
NXP TechSupport

Hi EdSutter

   If you understand the IP / AXI, you will not ask the ITCM, as it is no relationship with the ITCM in your related register, it is the IP commander.

   To be easy understand, AXI, you can think the address is the RT remap address, that's why you find other BR number will locate the address above 0X80000000, which is the SEMC related remap address in the RT series.

    But, to the IP commander, the related address is totally no the RT related memory address, it is the external memory self address which will from 0.

   That's why it makes you confused, as BR4 support AXI, it use the RT memory map address, but BR8 can't support AXI, it just support IP, it use the external memory Nand flash chip self address, not the address 0 the nand flash address, not the RT remap address, RT remap address 0 is the iTCM, but to external nand flash, it is just the nandflash self address.

 

Wish it helps you!

If you still have questions about it, please kindly let me know!

Best Regards,

Kerry

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NXP TechSupport
NXP TechSupport

HI EdSutter,

  1. Please tell me how do you check the unused regions are marked "valid" in the SEMC space?

     Just debug the code, and check addres from 0x80000000?

  2. SEMC is remapped to 0X80000000, so it won't has conflict with the internal ITCM.

image.png

 

Wish it helps you!

If you still have questions about it, please kindly let me know!

Best Regards,

Kerry

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Senior Contributor II

I still don't understand why the final NAND section of SEMC is valid and mapped to address 0 when running with evkmimxrt1060_sdram_ini_dcd.c...

Regarding how I see this, just look at the bits in the BaseRegisters.  In the case of the NAND at 0, the valid bit in BR8 is set, and the BA bits indicate start address of 0.

What am I misunderstanding here?

Tx

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Senior Contributor II

Kerry,

That map just shows where the entire SEMC space can legally be placed.  I get that; but then there are several potential devices within that SEMC space (four banks of SDRAM, NOR, PSRAM, etc...) that can be mapped within that space.  The base registers of the SEMC allow me to set up the address ranges for the different devices.  I get that too.

The problem is the SDK-provided DCD file (evkmimxrt1060_sdram_ini_dcd.c) for SDRAM configuration sets up ALL of the devices with non-overlapping memory space, and it puts BR8 at address 0...

 

...
    /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
    0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
    /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */
    0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24,
    /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */
    0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24,
    /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
    0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
    /* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
    0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
    /* #1.100, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
    0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
    /* #1.101, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
    0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
    /* #1.102, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
    0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
    /* #1.103, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
    0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
    /* #1.104, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
    0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
    /* #1.105, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
    0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
    /* #1.106, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
    0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
    /* #1.107, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
    0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
...

 

Notice that all the BR registers have the LSB (Valid bit) set; but worse than that, BR8 has a starting address of zero.  I need to understand this because I am having trouble (see this post) with SEMC devices.

By the way, this is the code that I use to display the runtime mapping of the SEMC devices (but AFAIK this doesn't have anything to do with the above DCD block setting up all SEMC devices valid)...

uint32_t
emcsize(uint32_t br)
{
    uint32_t ms = ((br & 0x0000003e) >> 1);
    uint32_t size = 0x1000;

    while(ms) {
        size *= 2;
        ms--;
    }
    return(size);
}

 

uint32_t base, size, end;

for(int i=0;i<9;i++) {
    base = SEMC->BR[i] & 0xfffff000;
    size = emcsize(SEMC->BR[i]);
    end = base + size - 1;
    if (SEMC->BR[i] & 1) // Valid?
        printf("%-6s: 0x%08x-0x%08x\n",emcspace[i],base,end);
    else
        printf("%-6s: invalid\n",emcspace[i]);
}

Thanks

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