Now we want to use SEMC to connect i.MX-RT1050 and FPGA.
The interface to FPGA is considering general parallel connection using address lines and data lines.
It is an interface where address lines and data lines are completely separated.
It has almost the same interface as legacy SRAM and parallel NOR-flash.
*For example : http://www.issi.com/WW/pdf/IS29GL256_128.pdf
In the i.MX RT1050 processor reference manual, the NOR flash interface seems to be appropriate.
However, in this community post, the Pseudo SRAM interface is often chosen for some reason.
Should we choose Pseudo SRAM interface too?
Theare is another question.
This is a common question for NOR interface and pseudo SRAM interface.
What is the COL(column address bit width) in NOR/SRAM control register 0 ?
Use recommended signals connection table in section 25.4.3 (Pin Mux in SEMC) in the
Reference Manual for NOR / SRAM.
Bit field COL of SRAM control register 0 (SRAMCR0) is not used, may be zero.
Burst Length BL bit field should be zero.