What do I need to set to make a second QSPI appear in the 106x's AHB memory region?

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What do I need to set to make a second QSPI appear in the 106x's AHB memory region?

Contributor III

Hi everyone,

Even though I can access a second QSPI in my RT1061 device via DMA (on the IP bus) perfectly well, I can't seem to see it mapped into the AHB memory range.

  • My main startup header has:
    • .sflashA1Size = 16u * 1024u * 1024u,
    • .sflashB1Size = 16u * 1024u * 1024u,
  • My board.c region has:
    • MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
    • MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);

I'm trying to access the second QSPI at 0x61000000, but am not seeing anything there.

Is there some other setting that is needed to make the B1 QSPI readable in the AHB address space?

Alternatively, if you know what registers control how the AHB maps different flash devices onto the AHB 0x60000000+ address range, please say, because I've gone through the chapters in the Reference Manual looking for this but am none the wiser. Knowing what these registers are should at least help me debug this issue at a low level (and maybe even fix it).

Thanks, Nick Pelling

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NXP TechSupport
NXP TechSupport

Hello Nick, 

How did you connect both memories into the RT? Did you connect both of them to the same FlexSPI interface? Or did you connect each memory to a FlexSPI interface? 


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Contributor III

Hi @victorjimenez 

I managed to sort the problem out on Friday. Once I figured out that the flash size (and hence the AHB memory layout) was defined by the FlexSPI instance's four FLSHCR0[port] hardware registers, it didn't take long to work out that the structs I was passing down to FLEXSPI_SetFlashConfig() were slightly incorrect. All sorted!

Cheers, Nick