Watchdog doesn't reset MIMXRT1060xxx5A

[thijsnulle]

I am trying to implement the watchdog timer on the iMX RT 1062 OEM (https://www.embeddedartists.com/products/imx-rt1062-oem/), but I can't flash the wdog example project to the board, this might be because of some memory addresses being wrong in the embedded artists version.

Whenever I am flashing the example project it did compile, but I couldn't flash it with JLink. I got this error message: 

```

Thu Mar 18, 2021 16:31:44: IAR
Embedded Workbench 8.50.9 (C:\
Program Files (x86)\IAR Systems\
Embedded Workbench 8.4_2\arm\bin\
armproc.dll)
Thu Mar 18, 2021 16:31:44: Loaded
macro file: C:\Program Files (x86)\IAR
Systems\Embedded Workbench 8.4_2\
arm\config\debugger\NXP\
iMXRT.dmac
Thu Mar 18, 2021 16:31:44: Loaded
macro file: C:\Program Files (x86)\IAR
Systems\Embedded Workbench 8.4_2\
arm\config\debugger\NXP\
iMXRT_Trace.dmac
Thu Mar 18, 2021 16:31:44: Loaded
macro file: C:\Program Files (x86)\IAR
Systems\Embedded Workbench 8.4_2\
arm\config\flashloader\NXP\
FlashIMXRT1060_FlexSPI.mac
Thu Mar 18, 2021 16:31:44: JLINK
command: ProjectFile = D:\work\forze\
sdk newest\boards\evkmimxrt1060\
driver_examples\wdog\iar\settings\
wdog01_flexspi_nor_debug.jlink, return
= 0
Thu Mar 18, 2021 16:31:44: Device
"MIMXRT1062XXX6A" selected.
Thu Mar 18, 2021 16:31:44: DLL version:
V6.88b, compiled Nov 27 2020 15:44:11
Thu Mar 18, 2021 16:31:44: Firmware:
J-Link V11 compiled Feb  4 2021
12:59:17
Thu Mar 18, 2021 16:31:44: Selecting
SWD as current target interface.
Thu Mar 18, 2021 16:31:44: JTAG speed
is initially set to: 32 kHz
Thu Mar 18, 2021 16:31:44: InitTarget()
start
Thu Mar 18, 2021 16:31:44: InitTarget()
Thu Mar 18, 2021 16:31:44: _TargetHalt:
CPU halted
Thu Mar 18, 2021 16:31:44: InitTarget()
end
Thu Mar 18, 2021 16:31:44: Found
SW-DP with ID 0x0BD11477
Thu Mar 18, 2021 16:31:44: DPIDR:
0x0BD11477
Thu Mar 18, 2021 16:31:44: Scanning AP
map to find all available APs
Thu Mar 18, 2021 16:31:44: AP[1]:
Stopped AP scan as end of AP map
has been reached
Thu Mar 18, 2021 16:31:44: AP[0]:
AHB-AP (IDR: 0x04770041)
Thu Mar 18, 2021 16:31:44: Iterating
through AP map to find AHB-AP to use
Thu Mar 18, 2021 16:31:44: AP[0]: Core
found
Thu Mar 18, 2021 16:31:44: AP[0]:
AHB-AP ROM base: 0xE00FD000
Thu Mar 18, 2021 16:31:44: CPUID
register: 0x411FC271. Implementer
code: 0x41 (ARM)
Thu Mar 18, 2021 16:31:44: Found
Cortex-M7 r1p1, Little endian.
Thu Mar 18, 2021 16:31:45: FPUnit: 8
code (BP) slots and 0 literal slots
Thu Mar 18, 2021 16:31:45: CoreSight
components:
Thu Mar 18, 2021 16:31:45: ROMTbl[0]
@ E00FD000
Thu Mar 18, 2021 16:31:45:
ROMTbl[0][0]: E00FE000, CID:
B105100D, PID: 000BB4C8 ROM Table
Thu Mar 18, 2021 16:31:45: ROMTbl[1]
@ E00FE000
Thu Mar 18, 2021 16:31:45:
ROMTbl[1][0]: E00FF000, CID:
B105100D, PID: 000BB4C7 ROM Table
Thu Mar 18, 2021 16:31:45: ROMTbl[2]
@ E00FF000
Thu Mar 18, 2021 16:31:45:
ROMTbl[2][0]: E000E000, CID:
B105E00D, PID: 000BB00C SCS-M7
Thu Mar 18, 2021 16:31:45:
ROMTbl[2][1]: E0001000, CID:
B105E00D, PID: 000BB002 DWT
Thu Mar 18, 2021 16:31:45:
ROMTbl[2][2]: E0002000, CID:
B105E00D, PID: 000BB00E FPB-M7
Thu Mar 18, 2021 16:31:45:
ROMTbl[2][3]: E0000000, CID:
B105E00D, PID: 000BB001 ITM
Thu Mar 18, 2021 16:31:45:
ROMTbl[1][1]: E0041000, CID:
B105900D, PID: 001BB975 ETM-M7
Thu Mar 18, 2021 16:31:45:
ROMTbl[1][2]: E0042000, CID:
B105900D, PID: 004BB906 CTI
Thu Mar 18, 2021 16:31:45:
ROMTbl[0][1]: E0040000, CID:
B105900D, PID: 000BB9A9 TPIU-M7
Thu Mar 18, 2021 16:31:45:
ROMTbl[0][2]: E0043000, CID:
B105F00D, PID: 001BB101 TSG
Thu Mar 18, 2021 16:31:45: Cache:
Separate I- and D-cache.
Thu Mar 18, 2021 16:31:45: I-Cache L1:
32 KB, 512 Sets, 32 Bytes/Line, 2-Way
Thu Mar 18, 2021 16:31:45: D-Cache L1:
32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Thu Mar 18, 2021 16:31:45: Reset: Halt
core after reset via
DEMCR.VC_CORERESET.
Thu Mar 18, 2021 16:31:45: Reset:
Reset device via
AIRCR.SYSRESETREQ.
Thu Mar 18, 2021 16:31:45: Hardware
reset with strategy 0 was performed
Thu Mar 18, 2021 16:31:45: Initial reset
was performed
Thu Mar 18, 2021 16:31:46: Disable
watchdog ...
Thu Mar 18, 2021 16:31:47: FLASH
MAC:____Configure ITCM, DTCM and
OCRAM____
Thu Mar 18, 2021 16:31:47: 3340 bytes
downloaded and verified (18.96
Kbytes/sec)
Thu Mar 18, 2021 16:31:47: Loaded
debugee: C:\Program Files (x86)\IAR
Systems\Embedded Workbench 8.4_2\
arm\config\flashloader\NXP\
FlashIMXRT1060_FlexSPI.out
Thu Mar 18, 2021 16:31:47: Target reset
Thu Mar 18, 2021 16:31:47: Unloaded
macro file: C:\Program Files (x86)\IAR
Systems\Embedded Workbench 8.4_2\
arm\config\flashloader\NXP\
FlashIMXRT1060_FlexSPI.mac
Thu Mar 18, 2021 16:31:47: The flash
loader program reported an error.
Thu Mar 18, 2021 16:31:50: IAR
Embedded Workbench 8.50.9 (C:\
Program Files (x86)\IAR Systems\
Embedded Workbench 8.4_2\arm\bin\
armproc.dll)

```

After I couldn't figure out how to run the example project, I tried to change the Config_MPU method since I thought it had something to do with memory. I changed the method into this:

void BOARD_ConfigMPU(void)
{
    /* Disable I cache and D cache */
    if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
    {
        SCB_DisableICache();
    }
    if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
    {
        SCB_DisableDCache();
    }

    /* Disable MPU */
    ARM_MPU_Disable();

    /* MPU configure:
     * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
     * SubRegionDisable, Size)
     * API in mpu_armv7.h.
     * param DisableExec       Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
     * disabled.
     * param AccessPermission  Data access permissions, allows you to configure read/write access for User and
     * Privileged mode.
     *      Use MACROS defined in mpu_armv7.h:
     * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
     * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
     *  TypeExtField  IsShareable  IsCacheable  IsBufferable   Memory Attribtue    Shareability        Cache
     *     0             x           0           0             Strongly Ordered    shareable
     *     0             x           0           1              Device             shareable
     *     0             0           1           0              Normal             not shareable   Outer and inner write
     * through no write allocate
     *     0             0           1           1              Normal             not shareable   Outer and inner write
     * back no write allocate
     *     0             1           1           0              Normal             shareable       Outer and inner write
     * through no write allocate
     *     0             1           1           1              Normal             shareable       Outer and inner write
     * back no write allocate
     *     1             0           0           0              Normal             not shareable   outer and inner
     * noncache
     *     1             1           0           0              Normal             shareable       outer and inner
     * noncache
     *     1             0           1           1              Normal             not shareable   outer and inner write
     * back write/read acllocate
     *     1             1           1           1              Normal             shareable       outer and inner write
     * back write/read acllocate
     *     2             x           0           0              Device              not shareable
     *  Above are normal use settings, if your want to see more details or want to config different inner/outter cache
     * policy.
     *  please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
     * param SubRegionDisable  Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
     * param Size              Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
     * mpu_armv7.h.
     */

    /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);

    /* Region 1 setting: Memory with Device type, not shareable,  non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

/* Region 2 setting */
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
    /* Setting Memory with Normal type, not shareable, outer/inner write back. */
    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
#else
    /* Setting Memory with Device type, not shareable, non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_8MB);
#endif

    /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

    /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);

    /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);

    /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);

    /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);

/* The define sets the cacheable memory to shareable,
 * this suggestion is referred from chapter 2.2.1 Memory regions,
 * types and attributes in Cortex-M7 Devices, Generic User Guide */
#if defined(SDRAM_IS_SHAREABLE)
    /* Region 8 setting: Memory with Normal type, shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
#else
    /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
#endif

    /* Region 9 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
     * accessed by cache can be put here */
    /* Memory with Normal type, not shareable, non-cacheable */
    MPU->RBAR = ARM_MPU_RBAR(9, 0x81E00000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);

    /* Enable MPU */
    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);

    /* Enable I cache and D cache */
    SCB_EnableDCache();
    SCB_EnableICache();
}

This allowed me to flash the code to the board and everything worked fine until the reset. Whenever I uncommented the WDOG_Refresh method inside the infinite loop of the example project, the interrupt handler did get called but nothing after.

If I paused the debugger once the reset should have happened it showed that the board was in an infinite loop in disassembly, so I think the reset failed.

If I resetted the board manually, it did show the lights flickering indicating something happened, but nothing got printed to putty if I did reset it.

I am curious to see where the problem could lie and where I should look next. If this is a known issue, what could I try to fix it. Thanks in advance.

[mjbcswitzerland]

Hi

Try this on your board:

https://www.utasker.com/iMX/iMX_RT1062_OEM.html

Test the reset and watchdog on the CLI that appears on LPUART or via USB-CDC (move to the administrator menu where you will find "reset" to test warm resets, "boot" to reset to the boot loader  or "fboot" to reset to its fall-back loader (allowing updates of the serial loader) and "wdog" to test the watchdog operation.

If something doesn't work it may signal a HW issue. If all works it means that your present issue is firmware related.

See also this video for an analysis of working with encrypted boot loading with your EA OEM board: https://youtu.be/o7hQbOqhJoc

If you are doing professional development register for the uTasker project (including simulation of the EA IOM module) for a complete out-of-the box solution to avoid learning curves and needing to port examples to the HW.

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]
Contact me by personal message or on the uTasker web site to discuss professional training, solutions to problems or rapid product development requirements

For professionals searching for faster, problem-free Kinetis and i.MX RT 10xx developments the uTasker project holds the key: https://www.utasker.com/iMX/RT1060.html