We are not sure about the VDDA_ADC_3P3 Pin of the RT1062.
On some places in the data sheet, it is noted that the difference to VDDA may not exceed 100mV (220.127.116.11.1). On other places, it is noted that VDDA_ADC_3P3 may not be powered when other SoC supplies are off (4.1.3).
Again in another place (18.104.22.168) it is noted, that this supply is not part of the power supply sequence and may be powered at any time.
In the conclusion, does this mean that VDDA_ADC_3P3 needs to be connected to the main VDD (DCDC_IN), over some filter elements, or can it be supplied by an exact 3V3 reference which is enabled after the main VDD has powered up?
The latter variant has big advantages in terms of ripple voltage and exactness of the reference, as VREFH is directly connected to VDDA_ADC_3P3 internally in the RT1062.
This information is crucial to our design, so we would be very glad about a precise answer.
Thanks for your reply and best regards,
I have same question as in original post: can VDDA_ADC_3P3 be powered on prior to other RT1060-series power supply rails?
Please clarify these statements. The EVK schematic does not answer this question because it connects VDDA_ADC_3P3 directly to other power supplies. This is not the preferred solution for our design.
For the detail please refer to the shematic of the EVK. And for power supply decoupling recommendation Please refer to the hardware development guide for the MIMXRT1060 processor.
Have a nice day.