Using combined HyperFlash/HyperRAM with iMXRT1062

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Using combined HyperFlash/HyperRAM with iMXRT1062

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Zu
Contributor II

Hi,
We are planning to use a combined HyperFlash/HyperRAM chip from Cypress (the exact part name is I think S71KS512SC0) with imxRT1062.
As a result of using a combined chip, both memories will use the same FlexSPI interface but with different CS signals.

So far we have been using XIP for our project (with external HyperFlash and internal RAM memory only), but I found this post Question about Using HyperRam and HyperFlash and based on that the XIP functionality is not available when using HyperRAM on the same FlexSPI bus as the HyperFlash. Can anyone confirm that this is the case for Cypress S71KS512SC0 also? 

If running in XIP mode is not an option - is it possible to boot from HyperFlash directly to this HyperRAM?
I am not concerned about the code size (it should fit into internal RAM as well), but we also have this big (~3MB) array stored in HyperFlash that is then used to perform some calculations. 
Could someone propose what the best scenario for this combination could look like?

Any references to guides, application notes, on how to set up this HyperFlash with HyperRAM highly welcome!

Thanks in advance,
Zuza

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Can anyone confirm that this is the case for Cypress S71KS512SC0 also?
-- Yes, it's.
2) If running in XIP mode is not an option - is it possible to boot from HyperFlash directly to this HyperRAM?
-- No, I'm afraid not.
3) Could someone propose what the best scenario for this combination could look like?
-- It'd better to connect HyperFlash and HyperRAM to FlexSPI1 and FlexSPI2 respectively.
Have a great day,
TIC

 

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193 Views
Zu
Contributor II

Hi Tic,

thank you for your quick response! 

The problem with your suggestion is that this is a combined HyperRAM/HyperFlash chip (here is a link to the documentation: https://www.cypress.com/file/322936/download) 
So all the pins (except for the CS0 and CS1) are shared. Are you saying that it still can be connected to both FlexSPI1 and FlexSPI2?

greetings
Zuza

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,
Thanks for your reply.
1) So all the pins (except for the CS0 and CS1) are shared. Are you saying that it still can be connected to both FlexSPI1 and FlexSPI2?
-- No, let me clarify it, I'd like to suggest you connect HyperFlash and HyperRAM to FlexSPI1 and FlexSPI2 respectively instead of all the data pins (except for the CS0 and CS1) of HyperFlash and HyperRAM are shared.
Hope this is clear.
Have a great day,
TIC

 

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Zu
Contributor II

Hi Jeremy,

thank you for your response. From what I understand we cannot achieve what we initially planned with this shared HyperFlash and HyperRAM chip, as it only exposes a single interface for both memories.

I have got another question though - is it possible to use just the HyperRAM memory with "Load application to RAM" option from MCUExpresso?
I am aware of it being just a one-shot debugging option, but we would really like to test some parts of our application before changing the PCB design to use different Flash memory on a separate FlexSPI interface.
If yes - what should be done to configure the memory first?

thank you for your patience
Zuza

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,
Thanks for your reply.
1)Is it possible to use just the HyperRAM memory with the "Load application to RAM" option from MCUExpresso?
-- No, I'm afraid not.
2) I am aware of it is just a one-shot debugging option, but we would really like to test some parts of our application before changing the PCB design to use different Flash memory on a separate FlexSPI interface.
If yes - what should be done to configure the memory first?
-- Yes, you can set the Link Application to RAM feature to enable debug a project directly from RAM, just as the below figure shows.

Regarding your purpose, you can learn how to implement the RWW feature on the HyperFlash and HyperRAM that connects to the same FlexSPI port by referring to the application note.
Hope it helps.
TIC

 

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