Using RT1052 SDRAM config from EVK demo

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Using RT1052 SDRAM config from EVK demo

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variable_andrew
Senior Contributor I

Could you confirm if the Micron MT48LC16M16A2b4-6a can use the same config as the RT1052EVK's ISSI is42s16160j-6bli SDRAM?

ISSI datasheet: http://www.issi.com/WW/pdf/42-45S83200J-16160J.pdf

Micron: https://www.micron.com/products/dram/sdram/part-catalog/mt48lc16m16a2b4-6a 

They have the same memory / bank layout it appears... but:

I'm trying to test this Micron SDRAM on our board using the basic MCUXpresso SEMC demo:

SEMC_SDRAMReadWrite32Bit fails, but SEMC_SDRAMReadWrite16Bit and SEMC_SDRAMReadWrite8Bit both pass, so there's something specifically wrong w/ 32 bit writes/reads for us using the micron memory w/ the default EVK's SDRAM init.

Any thoughts on why just 32 bit would fail? 

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11 Replies

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bowerymarc
Contributor V

I had a similar issue with the EA RT1062 board which has micron SDRAM.  I think I discovered the issue.  In my case, I discovered that there were some discrepancies in the pinmux settings.  I discovered this by:

- instantiate the semc demo.

- go to the pinmux gui tool.  This will analyze the project and create pinmux settings.

- in your other project, check your pinmux settings.  Diff the pinmux.c file with the newly updated one in the semc demo.  You fill find they are different.  Correct the differences.

This fixed the problem for me.

Additionally, I instantiated the SEMC peripheral and chose "DCD" option, selected the 'demo board' settings, then added the flags to my project:

SKIP_SYSCLK_INIT
XIP_BOOT_HEADER_DCD_ENABLE=1

 This allowed me to use the SDRAM for, e.g. heap memory, and passed all the same tests, and allowed me to add more peripherals to my project.

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351 Views
bowerymarc
Contributor V

I'm having the same issue on the Embedded Artists RT1062 board, 32 bit not working, 16/8 bit working.   No further resolution?

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476 Views
variable_andrew
Senior Contributor I

A quick comparison shows these two SDRAM parts should be identical for the config used in the SEMC demo app...

Any hints / ideas from SDRAM experts on what could be causing uint32_t access to fail while uint16_t and uint8_t are working fine?

Screen Shot 2020-01-24 at 4.43.09 PM.png

status_t BOARD_InitSEMC(void)
{
    semc_config_t config;
    semc_sdram_config_t sdramconfig;
    uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;

    /* Initializes the MAC configure structure to zero. */
    memset(&config, 0, sizeof(semc_config_t));
    memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));

    /* Initialize SEMC. */
    SEMC_GetDefaultConfig(&config);
    config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
    SEMC_Init(SEMC, &config);

    /* Configure SDRAM. */
    sdramconfig.csxPinMux           = kSEMC_MUXCSX0;
    sdramconfig.address             = 0x80000000;
    sdramconfig.memsize_kbytes      = 32 * 1024; /* 32MB = 32*1024*1KBytes*/
    sdramconfig.portSize            = kSEMC_PortSize16Bit;
    sdramconfig.burstLen            = kSEMC_Sdram_BurstLen8;
    sdramconfig.columnAddrBitNum    = kSEMC_SdramColunm_9bit;
    sdramconfig.casLatency          = kSEMC_LatencyThree;
    sdramconfig.tPrecharge2Act_Ns   = 18; /* Trp 18ns */
    sdramconfig.tAct2ReadWrite_Ns   = 18; /* Trcd 18ns */
    sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
    sdramconfig.tWriteRecovery_Ns   = 12; /* 12ns */
    sdramconfig.tCkeOff_Ns =
        42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
    sdramconfig.tAct2Prechage_Ns       = 42; /* Tras 42ns */
    sdramconfig.tSelfRefRecovery_Ns    = 67;
    sdramconfig.tRefresh2Refresh_Ns    = 60;
    sdramconfig.tAct2Act_Ns            = 60;
    sdramconfig.tPrescalePeriod_Ns     = 160 * (1000000000 / clockFrq);
    sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
    sdramconfig.refreshUrgThreshold    = sdramconfig.refreshPeriod_nsPerRow;
    sdramconfig.refreshBurstLen        = 1;
    return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

476 Views
variable_andrew
Senior Contributor I

I'll add a note to this - so based on the tests, it seems that the controller manages reads/writes to SDRAM so long as the variable being read/written is uint8_t or uint16_t based, but fails for uint32_t. 

What is needed to enable the SDRAM controller to manage this?

476 Views
jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
I've attached two descriptors of the MT48LC16M16A2B4-6A and IS42S16160J. They can help you to adjust initialization function code.

DCD Descriptor
MT48LC16M16A2B4-6A

// Clock Init
// Init all clocks
*(uint32_t*)0x400FC068 = 0xffffffff;
*(uint32_t*)0x400FC06C = 0xffffffff;
*(uint32_t*)0x400FC070 = 0xffffffff;
*(uint32_t*)0x400FC074 = 0xffffffff;
*(uint32_t*)0x400FC078 = 0xffffffff;
*(uint32_t*)0x400FC07C = 0xffffffff;
*(uint32_t*)0x400FC080 = 0xffffffff;

//*(uint32_t*)0x400D8050 = 0x00000011;
//*(uint32_t*)0x400D8060 = 0x00000003;
//CCM_ANALOG->PLL_SYS = 0x00002001;
*(uint32_t*)0x400D8030 = 0x00002001;
// CCM_ANALOG->PFD528 = 0x001d0000;     //163Mhz
*(uint32_t*)0x400D8100 = 0x00230000;    //133Mhz
// CCM->CBBCDR = 0x000D8340;
*(uint32_t*)0x400FC014 = 0x00010D40;
//*(uint32_t*)0x400FC014 = 0x00050D40;
// SDRAM Init
// Configure IOMUXC for SDRAM 
*(uint32_t*)0x401F8014 = 0x00000000;
*(uint32_t*)0x401F8018 = 0x00000000;
*(uint32_t*)0x401F801C = 0x00000000;
*(uint32_t*)0x401F8020 = 0x00000000;
*(uint32_t*)0x401F8024 = 0x00000000;
*(uint32_t*)0x401F8028 = 0x00000000;
*(uint32_t*)0x401F802C = 0x00000000;
*(uint32_t*)0x401F8030 = 0x00000000;
*(uint32_t*)0x401F8034 = 0x00000000;
*(uint32_t*)0x401F8038 = 0x00000000;
*(uint32_t*)0x401F803C = 0x00000000;
*(uint32_t*)0x401F8040 = 0x00000000;
*(uint32_t*)0x401F8044 = 0x00000000;
*(uint32_t*)0x401F8048 = 0x00000000;
*(uint32_t*)0x401F804C = 0x00000000;
*(uint32_t*)0x401F8050 = 0x00000000;
*(uint32_t*)0x401F8054 = 0x00000000;
*(uint32_t*)0x401F8058 = 0x00000000;
*(uint32_t*)0x401F805C = 0x00000000;
*(uint32_t*)0x401F8060 = 0x00000000;
*(uint32_t*)0x401F8064 = 0x00000000;
*(uint32_t*)0x401F8068 = 0x00000000;
*(uint32_t*)0x401F806C = 0x00000000;
*(uint32_t*)0x401F8070 = 0x00000000;
*(uint32_t*)0x401F8074 = 0x00000000;
*(uint32_t*)0x401F8078 = 0x00000000;
*(uint32_t*)0x401F807C = 0x00000000;
*(uint32_t*)0x401F8080 = 0x00000000;
*(uint32_t*)0x401F8084 = 0x00000000;
*(uint32_t*)0x401F8088 = 0x00000000;
*(uint32_t*)0x401F808C = 0x00000000;
*(uint32_t*)0x401F8090 = 0x00000000;
*(uint32_t*)0x401F8094 = 0x00000000;
*(uint32_t*)0x401F8098 = 0x00000000;
*(uint32_t*)0x401F809C = 0x00000000;
*(uint32_t*)0x401F80A0 = 0x00000000;
*(uint32_t*)0x401F80A4 = 0x00000000;
*(uint32_t*)0x401F80A8 = 0x00000000;
*(uint32_t*)0x401F80AC = 0x00000000;
*(uint32_t*)0x401F80B0 = 0x00000010;
*(uint32_t*)0x401F80B4 = 0x00000000;
*(uint32_t*)0x401F80B8 = 0x00000000;

// PAD ctrl
*(uint32_t*)0x401F8204 = 0x000110F9;
*(uint32_t*)0x401F8208 = 0x000110F9;
*(uint32_t*)0x401F820C = 0x000110F9;
*(uint32_t*)0x401F8210 = 0x000110F9;
*(uint32_t*)0x401F8214 = 0x000110F9;
*(uint32_t*)0x401F8218 = 0x000110F9;
*(uint32_t*)0x401F821C = 0x000110F9;
*(uint32_t*)0x401F8220 = 0x000110F9;
*(uint32_t*)0x401F8224 = 0x000110F9;
*(uint32_t*)0x401F8228 = 0x000110F9;
*(uint32_t*)0x401F822C = 0x000110F9;
*(uint32_t*)0x401F8230 = 0x000110F9;
*(uint32_t*)0x401F8234 = 0x000110F9;
*(uint32_t*)0x401F8238 = 0x000110F9;
*(uint32_t*)0x401F823C = 0x000110F9;
*(uint32_t*)0x401F8240 = 0x000110F9;
*(uint32_t*)0x401F8244 = 0x000110F9;
*(uint32_t*)0x401F8248 = 0x000110F9;
*(uint32_t*)0x401F824C = 0x000110F9;
*(uint32_t*)0x401F8250 = 0x000110F9;
*(uint32_t*)0x401F8254 = 0x000110F9;
*(uint32_t*)0x401F8258 = 0x000110F9;
*(uint32_t*)0x401F825C = 0x000110F9;
*(uint32_t*)0x401F8260 = 0x000110F9;
*(uint32_t*)0x401F8264 = 0x000110F9;
*(uint32_t*)0x401F8268 = 0x000110F9;
*(uint32_t*)0x401F826C = 0x000110F9;
*(uint32_t*)0x401F8270 = 0x000110F9;
*(uint32_t*)0x401F8274 = 0x000110F9;
*(uint32_t*)0x401F8278 = 0x000110F9;
*(uint32_t*)0x401F827C = 0x000110F9;
*(uint32_t*)0x401F8280 = 0x000110F9;
*(uint32_t*)0x401F8284 = 0x000110F9;
*(uint32_t*)0x401F8288 = 0x000110F9;
*(uint32_t*)0x401F828C = 0x000110F9;
*(uint32_t*)0x401F8290 = 0x000110F9;
*(uint32_t*)0x401F8294 = 0x000110F9;
*(uint32_t*)0x401F8298 = 0x000110F9;
*(uint32_t*)0x401F829C = 0x000110F9;
*(uint32_t*)0x401F82A0 = 0x000110F9;
*(uint32_t*)0x401F82A4 = 0x000110F9;
*(uint32_t*)0x401F82A8 = 0x000110F9;

// Config SEMC Controller Registers
*(uint32_t*)0x402F0000 = 0x1000E000;//0x1000E000;
*(uint32_t*)0x402F0008 = 0x00030524;
*(uint32_t*)0x402F000C = 0x06030524;
*(uint32_t*)0x402F0010 = 0x8000001B;
*(uint32_t*)0x402F0014 = 0x90000021;
*(uint32_t*)0x402F0004 = 0x00000008;
*(uint32_t*)0x402F0040 = 0x00000B27;
*(uint32_t*)0x402F0044 = 0x00100100;
*(uint32_t*)0x402F0048 = 0x00020201;
*(uint32_t*)0x402F004C = 0x08193D0F;
*(uint32_t*)0x402F0080 = 0x00000021;
*(uint32_t*)0x402F0084 = 0x00888888;
*(uint32_t*)0x402F0094 = 0x00000002;
*(uint32_t*)0x402F0098 = 0x00000000;


*(uint32_t*)0x402F0000 = 0x10000004;//0x1000E000;
*(uint32_t*)0x402F0008 = 0x00030524;
*(uint32_t*)0x402F000C = 0x00030524;
*(uint32_t*)0x402F0010 = 0x8000001B;
*(uint32_t*)0x402F0014 = 0x8200001B;
*(uint32_t*)0x402F0018 = 0x8400001B;
*(uint32_t*)0x402F001C = 0x8600001B;
*(uint32_t*)0x402F0020 = 0x90000021;
*(uint32_t*)0x402F0024 = 0xA0000019;
*(uint32_t*)0x402F0028 = 0xA8000017;
*(uint32_t*)0x402F002C = 0xA900001B;
*(uint32_t*)0x402F0030 = 0x00000021;
*(uint32_t*)0x402F0004 = 0x000079A8;

*(uint32_t*)0x402F0040 = 0x00000F31;
*(uint32_t*)0x402F0044 = 0x00652922;
*(uint32_t*)0x402F0048 = 0x00010920;
*(uint32_t*)0x402F004C = 0x50210A08;

*(uint32_t*)0x402F0080 = 0x00000021;
*(uint32_t*)0x402F0084 = 0x00888888;
*(uint32_t*)0x402F0094 = 0x00000002;
*(uint32_t*)0x402F0098 = 0x00000000;

*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000F;
// wait_until 
(*(uint32_t*)0x402F003C & 0x01) != 0;

*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000C;
// wait_until 
(*(uint32_t*)0x402F003C & 0x01) != 0;

*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000C;
// wait_until
(*(uint32_t*)0x402F003C & 0x01) != 0;

*(uint32_t*)0x402F00A0 = 0x00000033;
*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000A;
// wait_until
(*(uint32_t*)0x402F003C & 0x01) != 0;

 *(uint32_t*)0x402F004C = 0x50210A09;‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍


DCD Descriptor
IS42S16160J

// Clock Init
// Init all clocks
*(uint32_t*)0x400FC068 = 0xffffffff;
*(uint32_t*)0x400FC06C = 0xffffffff;
*(uint32_t*)0x400FC070 = 0xffffffff;
*(uint32_t*)0x400FC074 = 0xffffffff;
*(uint32_t*)0x400FC078 = 0xffffffff;
*(uint32_t*)0x400FC07C = 0xffffffff;
*(uint32_t*)0x400FC080 = 0xffffffff;

//*(uint32_t*)0x400D8050 = 0x00000011;
//*(uint32_t*)0x400D8060 = 0x00000003;
//CCM_ANALOG->PLL_SYS = 0x00002001;
*(uint32_t*)0x400D8030 = 0x00002001;
// CCM_ANALOG->PFD528 = 0x001d0000;     //163Mhz
*(uint32_t*)0x400D8100 = 0x00230000;    //133Mhz
// CCM->CBBCDR = 0x000D8340;
*(uint32_t*)0x400FC014 = 0x00010D40;
//*(uint32_t*)0x400FC014 = 0x00050D40;
// SDRAM Init
// Configure IOMUXC for SDRAM 
*(uint32_t*)0x401F8014 = 0x00000000;
*(uint32_t*)0x401F8018 = 0x00000000;
*(uint32_t*)0x401F801C = 0x00000000;
*(uint32_t*)0x401F8020 = 0x00000000;
*(uint32_t*)0x401F8024 = 0x00000000;
*(uint32_t*)0x401F8028 = 0x00000000;
*(uint32_t*)0x401F802C = 0x00000000;
*(uint32_t*)0x401F8030 = 0x00000000;
*(uint32_t*)0x401F8034 = 0x00000000;
*(uint32_t*)0x401F8038 = 0x00000000;
*(uint32_t*)0x401F803C = 0x00000000;
*(uint32_t*)0x401F8040 = 0x00000000;
*(uint32_t*)0x401F8044 = 0x00000000;
*(uint32_t*)0x401F8048 = 0x00000000;
*(uint32_t*)0x401F804C = 0x00000000;
*(uint32_t*)0x401F8050 = 0x00000000;
*(uint32_t*)0x401F8054 = 0x00000000;
*(uint32_t*)0x401F8058 = 0x00000000;
*(uint32_t*)0x401F805C = 0x00000000;
*(uint32_t*)0x401F8060 = 0x00000000;
*(uint32_t*)0x401F8064 = 0x00000000;
*(uint32_t*)0x401F8068 = 0x00000000;
*(uint32_t*)0x401F806C = 0x00000000;
*(uint32_t*)0x401F8070 = 0x00000000;
*(uint32_t*)0x401F8074 = 0x00000000;
*(uint32_t*)0x401F8078 = 0x00000000;
*(uint32_t*)0x401F807C = 0x00000000;
*(uint32_t*)0x401F8080 = 0x00000000;
*(uint32_t*)0x401F8084 = 0x00000000;
*(uint32_t*)0x401F8088 = 0x00000000;
*(uint32_t*)0x401F808C = 0x00000000;
*(uint32_t*)0x401F8090 = 0x00000000;
*(uint32_t*)0x401F8094 = 0x00000000;
*(uint32_t*)0x401F8098 = 0x00000000;
*(uint32_t*)0x401F809C = 0x00000000;
*(uint32_t*)0x401F80A0 = 0x00000000;
*(uint32_t*)0x401F80A4 = 0x00000000;
*(uint32_t*)0x401F80A8 = 0x00000000;
*(uint32_t*)0x401F80AC = 0x00000000;
*(uint32_t*)0x401F80B0 = 0x00000010;
*(uint32_t*)0x401F80B4 = 0x00000000;
*(uint32_t*)0x401F80B8 = 0x00000000;

// PAD ctrl
*(uint32_t*)0x401F8204 = 0x000110F9;
*(uint32_t*)0x401F8208 = 0x000110F9;
*(uint32_t*)0x401F820C = 0x000110F9;
*(uint32_t*)0x401F8210 = 0x000110F9;
*(uint32_t*)0x401F8214 = 0x000110F9;
*(uint32_t*)0x401F8218 = 0x000110F9;
*(uint32_t*)0x401F821C = 0x000110F9;
*(uint32_t*)0x401F8220 = 0x000110F9;
*(uint32_t*)0x401F8224 = 0x000110F9;
*(uint32_t*)0x401F8228 = 0x000110F9;
*(uint32_t*)0x401F822C = 0x000110F9;
*(uint32_t*)0x401F8230 = 0x000110F9;
*(uint32_t*)0x401F8234 = 0x000110F9;
*(uint32_t*)0x401F8238 = 0x000110F9;
*(uint32_t*)0x401F823C = 0x000110F9;
*(uint32_t*)0x401F8240 = 0x000110F9;
*(uint32_t*)0x401F8244 = 0x000110F9;
*(uint32_t*)0x401F8248 = 0x000110F9;
*(uint32_t*)0x401F824C = 0x000110F9;
*(uint32_t*)0x401F8250 = 0x000110F9;
*(uint32_t*)0x401F8254 = 0x000110F9;
*(uint32_t*)0x401F8258 = 0x000110F9;
*(uint32_t*)0x401F825C = 0x000110F9;
*(uint32_t*)0x401F8260 = 0x000110F9;
*(uint32_t*)0x401F8264 = 0x000110F9;
*(uint32_t*)0x401F8268 = 0x000110F9;
*(uint32_t*)0x401F826C = 0x000110F9;
*(uint32_t*)0x401F8270 = 0x000110F9;
*(uint32_t*)0x401F8274 = 0x000110F9;
*(uint32_t*)0x401F8278 = 0x000110F9;
*(uint32_t*)0x401F827C = 0x000110F9;
*(uint32_t*)0x401F8280 = 0x000110F9;
*(uint32_t*)0x401F8284 = 0x000110F9;
*(uint32_t*)0x401F8288 = 0x000110F9;
*(uint32_t*)0x401F828C = 0x000110F9;
*(uint32_t*)0x401F8290 = 0x000110F9;
*(uint32_t*)0x401F8294 = 0x000110F9;
*(uint32_t*)0x401F8298 = 0x000110F9;
*(uint32_t*)0x401F829C = 0x000110F9;
*(uint32_t*)0x401F82A0 = 0x000110F9;
*(uint32_t*)0x401F82A4 = 0x000110F9;
*(uint32_t*)0x401F82A8 = 0x000110F9;

// Config SEMC Controller Registers
*(uint32_t*)0x402F0000 = 0x1000E000;//0x1000E000;
*(uint32_t*)0x402F0008 = 0x00030524;
*(uint32_t*)0x402F000C = 0x06030524;
*(uint32_t*)0x402F0010 = 0x8000001B;
*(uint32_t*)0x402F0014 = 0x90000021;
*(uint32_t*)0x402F0004 = 0x00000008;
*(uint32_t*)0x402F0040 = 0x00000B27;
*(uint32_t*)0x402F0044 = 0x00100100;
*(uint32_t*)0x402F0048 = 0x00020201;
*(uint32_t*)0x402F004C = 0x08193D0F;
*(uint32_t*)0x402F0080 = 0x00000021;
*(uint32_t*)0x402F0084 = 0x00888888;
*(uint32_t*)0x402F0094 = 0x00000002;
*(uint32_t*)0x402F0098 = 0x00000000;


*(uint32_t*)0x402F0000 = 0x10000004;//0x1000E000;
*(uint32_t*)0x402F0008 = 0x00030524;
*(uint32_t*)0x402F000C = 0x00030524;
*(uint32_t*)0x402F0010 = 0x8000001B;
*(uint32_t*)0x402F0014 = 0x8200001B;
*(uint32_t*)0x402F0018 = 0x8400001B;
*(uint32_t*)0x402F001C = 0x8600001B;
*(uint32_t*)0x402F0020 = 0x90000021;
*(uint32_t*)0x402F0024 = 0xA0000019;
*(uint32_t*)0x402F0028 = 0xA8000017;
*(uint32_t*)0x402F002C = 0xA900001B;
*(uint32_t*)0x402F0030 = 0x00000021;
*(uint32_t*)0x402F0004 = 0x000079A8;

*(uint32_t*)0x402F0040 = 0x00000F31;
*(uint32_t*)0x402F0044 = 0x00652922;
*(uint32_t*)0x402F0048 = 0x00010920;
*(uint32_t*)0x402F004C = 0x50210A08;

*(uint32_t*)0x402F0080 = 0x00000021;
*(uint32_t*)0x402F0084 = 0x00888888;
*(uint32_t*)0x402F0094 = 0x00000002;
*(uint32_t*)0x402F0098 = 0x00000000;

*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000F;
// wait_until 
(*(uint32_t*)0x402F003C & 0x01) != 0;

*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000C;
// wait_until 
(*(uint32_t*)0x402F003C & 0x01) != 0;

*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000C;
// wait_until
(*(uint32_t*)0x402F003C & 0x01) != 0;

*(uint32_t*)0x402F00A0 = 0x00000033;
*(uint32_t*)0x402F0090 = 0x80000000;
*(uint32_t*)0x402F009C = 0xA55A000A;
// wait_until
(*(uint32_t*)0x402F003C & 0x01) != 0;

 *(uint32_t*)0x402F004C = 0x50210A09;‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

TIC

 

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variable_andrew
Senior Contributor I

Thanks for the descriptors- they both appear to be the exact same.

This lines up with what i've found as well (see post below), but these are different from the evkbimxrt1050_semc demo. 

If I simply make a project that runs the descriptor you provided, and then i do 0x1000 writes / reads (similar to the semc demo), it appears to work for uint32_t now (in addition to uinr16_t. 
So I assume I should be using these timings now. For these, I have a few questions:

1. Can you help me understand why these descriptors enable all of the clocks? (i assume I should just be fine enabling the following in my code:

  CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]);
  CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]);

2. Why are the timings slightly different from the semc demo even for the same ISSI part?

3. Could you possibly enlighten me on which pins are required / used when doing 32bit accesses but not required for 16bit? Or are the same pins used and just timing is different between the access sizes?

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476 Views
jeremyzhou
NXP TechSupport
NXP TechSupport

Hi ,

Thanks for your reply.
1. Can you help me understand why these descriptors enable all of the clocks? (i assume I should just be fine enabling the following in my code:

  CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]);
  CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]);
-- In my opinion, the above two lines are enough to enable the clock of the SEMC module.
2. Why are the timings slightly different from the SEMC demo even for the same ISSI part?
-- The descriptors are used to generate the DCD bin file, definitely, it wouldn't be as same as the SEMC demo.
3. Could you possibly enlighten me on which pins are required / used when doing 32bit accesses but not required for 16bit? Or are the same pins used and just timing is different between the access sizes?
-- The pins connection is unnecessary to change to suit for different bit length read and write, however, in my opinion, the timing sequence would be a bit different.

TIC

 

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476 Views
variable_andrew
Senior Contributor I

jeremyzhou‌ -

We put together a few more boards, populated them with the ISSI SDRAM, and the semc_demo app works on all the others, so will move forward with the ISSI part for now. 

476 Views
variable_andrew
Senior Contributor I

thanks jeremyzhou‌, 

Could you also provide insight on why SDRAM doesn't work when doing resets (see post above - i think it's date-stamped before your response, but only got approved by moderators much later)?

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476 Views
variable_andrew
Senior Contributor I

Actually - testing with the descriptors worked for me for a few times, but eventually 32 bit accesses begin to fail as well, giving read output like so (instead of 0, 1, 2, 3, 4, ...: 

Screen Shot 2020-01-27 at 3.10.19 PM.png

What I found was that if I don't set "Reset on Connect" in the LinkServer Debugger options - then 32 bit accesses work when I re-run the app, but if I do set "Reset on Connect", then 32 bit accesses fail...

Further testing shows that if I just write garbage to SDRAM, and then read back - then subsequent writes and reads work to areas that had previously been accessed (on the MT device)... 

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variable_andrew
Senior Contributor I

how do i remove the need to moderate every post? 

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