Understanding ADC + ADC-ETC

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Understanding ADC + ADC-ETC

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Senior Contributor I

Hello,

I am trying to understand the ADC and ADC-ETC peripheral and to configure them with MCUXpresso Tools v7. I have read the reference manual and a lot of posts but I still need some more information.

I have addeded the peripheral drivers ADC1, ADC2 and ADC_ETC to my MCUXpresso peripherals tool.

****

Question 1:

pastedImage_1.png

Hovering above this check box tells me that checking it will optimize ADC start up time, but how much faster will it be if I enable it?

The reference manual states

pastedImage_2.png

, but it does not tell me how much faster it will be?

****

Question 2:

pastedImage_3.png

How much higher is the ADC clock? The "normal" frequency is 10 MHz correct?

****

Question 3:

About the low power mode the pseudo-code example (60.6.1.2) states in a comment that the low power mode lowers the maximum clock speed. Does it more? To which frequency does it lower the clock speed? If this one lowers the clock speed then selecting "high speed" and "low power" makes no sense right?

****

Question 4:

The ADC averaging of 4 samples is just a arithmetic average (e.g. Result = (Measurement1 + Measurement2 + Measurement3 + Measurement4)/4) right?

****

Question 5:

I want all channels of the ADCs to be controlled by ADC-ETC, but if I add more than one channel with the channel number to "CHANNEL_DRIVEN_BY_ADC_ETC" I get a warning that there are some duplicated ADC channels in the configuration. Do I have to set every channel with "CHANNEL_DRIVEN_BY_ADC_ETC" or just leave the "Channels configuration" empty?

pastedImage_4.png

**** After here ADC-ETC questions

Question 6:

The Trigger group depends on the selected Trigger source. If I hover above the Sync mode checkbox I can see that there are couples wich can be triggered from the same trigger.

I set up Trigger group 0 and now I want to also Trigger group 4 in sync to it. For that I have to set up a new XBARA Trigger configuration where I choose XBAR1_TRIG,0 as Trigger source and I set the Sync mode.

pastedImage_5.png

In the Trigger source field there is the entry "0 >> LOGIC_LOW" which suggests that the trigger is connected to GND. Do I have to be concerned about that or does it not matter?

**** Question 7:

The boxes "Desired initial delay" and "Desired interval delay"

pastedImage_6.png

have to be set to at least 1 tick. The reference manual entry to ETC_TRIG0 Counter Register does not mention that the counter has to be set at least to 1 tick.

pastedImage_7.png

Is it necessary to set it to 1 or is it allowed to be zero?

Hint to the MCUXpresso Config Tools Development Team: The text "Real interval delay" is used for the "Desired initial delay" settings and I think it should be "Real initial delay".

**** Question 8:

I want to measure the same input 8 times and at the end the DONE0 interrupt should be fired. I set the Chain configuration to

pastedImage_8.png

And after triggering once it will do chain 0, after chain 0 finished it will automatically do chain 1, then chain 2.... correct?

Will the data be stored in TRIG0_RESULT_1_0 DATA0 to TRIG0_RESULT_7_6 DATA7 or will every chain write the result of the measurement to TRIG0_RESULT_1_0 DATA0 because I selected "Conversion control group Group 0" for every chain?

**** Question 9:

What does the entry "Conversion control group" do?

**** Question 10:

If I want to sample one channel (e.g. ADC1 IN 14) 20 times, store the data to a buffer in RAM and after the 20th sample has been measured it shoud fire an interrupt? There should be no CPU intervention everything should be done in hardware until the interrupt condition is reached.

Do I have to use this method and emulate Scan Mode or is there another way?

Kind regards,

Stefan

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NXP Employee
NXP Employee

Hi Stefan,

1) When you have selected Asynchronous Clock as the clock source and then check the checkbox "Start asynchronous clock output", you are able to see the change in the "Resulting conversion time" info item below the "Conversion" configuration structure (above "Result correction" configuration structure).  

2) When you want to run the ADC at the highest speed so you can choose some other clock source like you say.

And you can find information about ranges in the datasheet in chapter "Electrical characteristics" -> "Analog" -> "A/D converter". Screenshots below are taken from https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf 

pastedImage_1.png

pastedImage_2.png

As you can see typical value of Asynchronous clock in high speed is 20 MHz, other clock source ranges are in the table first table.  

3) You're right the combination of bitfields ADHSC = 1 and ADLPC =1 is nonsense, so it is not in the datasheet also as you can see in the first table above.

7) OK, "Desired initial delay" value can be 0.

But for the Interval it doesn't make sense to start next conversion in chain without delay, it can only abort previous undone conversion or leads into the error interrupt.  

Hope it will helps you

Jiri

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NXP TechSupport
NXP TechSupport

Hi Stefan Mitterhauser,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.

For ADC questions
1 Hovering above this checkbox tells me that checking it will optimize ADC startup time, but how much faster will it be if I enable it?
-- The Asynchronous clock is selected as the clock source of the ADC will optime ADC start time, it's nothing related to the ADACKEN setting.

pastedImage_1.png
2. The High-Speed configuration allows the ADC can work with the higher clock.
3) I've not found the pseudo-code example code in the RM of RT1050, whether you can attach the codes here.
4) The ADC averaging of 4 samples is just a arithmetic average (e.g. Result = (Measurement1 + Measurement2 + Measurement3 + Measurement4)/4) right?
-- Yes.
5) These warnings just remind you to select the ADC sample channel prudently to avoid select duplicated ADC channels

TIC

 

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Senior Contributor I

Hello,

thank you for your answers!

1) The checkbox "Start asynchronous clock output" will be stored in the ADC1_config structure 

.enableAsynchronousClockOutput = true,

which will be set in the function ADC_Init

 if (config->enableAsynchronousClockOutput)
    {
        tmp32 |= ADC_GC_ADACKEN_MASK;
    }

so this option sets the ADACKEN bit in the register.

How does the peripheral optimize start up time and how much faster will it be?

*********************

2. The High-Speed configuration allows the ADC can work with the higher clock.

So I have to provide the higher clock myself with IPG_CLK_ROOT? What is the minimum frequency where I have to activate the High-Speed configuration for proper work?

*********************

3) I've not found the pseudo-code example code in the RM of RT1050, whether you can attach the codes here.

Here the code example:

pastedImage_11.png

*******************

7) Is it necessary to set it to 1 or is it allowed to be zero?

-- It allows being zero actually.

Okay I'll add it to my list over on the MCUXpresso Config Tools post.

Kind regards,

Stefan

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NXP TechSupport
NXP TechSupport

Hi Stefan Mitterhauser,

Thanks for your reply.
1) How does the peripheral optimize startup time and how much faster will it be?
-- Please check the below figure.

pastedImage_1.png
2) I think Jiri Chvatik already gived a detail clarification for question 2 & 3.

TIC

 

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Senior Contributor I

Thank you Jeremy and Jiri!
That was the connection I was missing to understand the peripherals.

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NXP Employee
NXP Employee

Hi Stefan,

1) When you have selected Asynchronous Clock as the clock source and then check the checkbox "Start asynchronous clock output", you are able to see the change in the "Resulting conversion time" info item below the "Conversion" configuration structure (above "Result correction" configuration structure).  

2) When you want to run the ADC at the highest speed so you can choose some other clock source like you say.

And you can find information about ranges in the datasheet in chapter "Electrical characteristics" -> "Analog" -> "A/D converter". Screenshots below are taken from https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf 

pastedImage_1.png

pastedImage_2.png

As you can see typical value of Asynchronous clock in high speed is 20 MHz, other clock source ranges are in the table first table.  

3) You're right the combination of bitfields ADHSC = 1 and ADLPC =1 is nonsense, so it is not in the datasheet also as you can see in the first table above.

7) OK, "Desired initial delay" value can be 0.

But for the Interval it doesn't make sense to start next conversion in chain without delay, it can only abort previous undone conversion or leads into the error interrupt.  

Hope it will helps you

Jiri

View solution in original post

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NXP TechSupport
NXP TechSupport

Hi Stefan Mitterhauser,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Before answering your question, I was wondering if you can share the MEX file of your project, as it can help me to understand your question correctly and figure it out efficiently.
Looking forward to your reply.

TIC

 

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Senior Contributor I

Hello jeremy,

I did not save the MEX file but I tried to recreated it. It is attached to this post.

Update to Question 9:

I understand now that the Conversion control group selects the ADCx_HCn and the corresponding ADCx_Rn registers for the measurement.

But as I mention in this post, I think that there is something wrong with the selectable groups because there are no ADCx_HC8 to ADCx_HC15 registers for the IMXRT1020.

I did not know where to post what and some of the questions fit into the MCUXpresso Config Tools forum and some here for general information so there are some questions duplicated in these three posts:

Kind regards,

Stefan

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NXP TechSupport
NXP TechSupport

Hi Stefan Mitterhauser,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
For ADC_ETC questions
5) Do I have to be concerned about that or does it not matter?
-- The trigger source means the external triggers from the XBAR module.
7) Is it necessary to set it to 1 or is it allowed to be zero?
-- It allows being zero actually.
8) Data be stored in TRIG0_RESULT_1_0 DATA0 to TRIG0_RESULT_7_6 DATA7
10) Regarding to your purpose, it's a bit easy than the emulate Scan Mode, as the sampled ADC channel keeps the same, the general DMA feature is enough to implement it.

 

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