UART_CLK_ROOT default speed

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UART_CLK_ROOT default speed

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Specialist V

Hi All

In the IMXRT1020 users manual the default UART_CLK_ROOT speed after POR is specified as being 4MHz (max 80MHz).

pastedImage_1.png

However I haven't been able to work out where this value comes from.

The clock si derived by default from PLL3/6 (i.e. 80MHz) and all further dividers default to /1. To default to 4Mz the PLL3/6 clock must be divided by 20, which could only take place in CSCDR[UART_CLK_PODF], which however defaults to /1.

Is this 4MHz default value incorrect or is there another explanation as to what is controlling it by default?

Regards

Mark

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NXP TechSupport
NXP TechSupport

Hi Mark Butcher ,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
From the attachment, we can find that the clock module boot from the on-chip oscillator 24Mhz initially, so the default UART clock = 24 MHz/6 =4 MHz.
Hope this is clear.

pastedImage_1.png

pastedImage_2.png

Have a great day,
TIC

 

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Specialist V

Hi

Thanks, that would make sense - but there is a discrepancy between your diagram and the user manual. The user manual shows pll3_sw_clk to be derived from PLL3 (480MHz) - giving a default UART clock of 480/6 = 80MHz:

pastedImage_2.png

pastedImage_3.png

Your diagram shows it being derived from the bypassed pll3 source (24MHz) which would indeed give the 4MHz.

However, the bypass is controlled by pll3_sw_clk_sel in CCM_CCSR:

pastedImage_4.png

which defaults to '0' -not bypassed:

pastedImage_5.png

Furthermore bypassing PLL3 is stated as only to be used for test purposes.

Therefore you diagram looks to not represent the default (according to the user's manual) and also to be using a setting that should not be used for normal purposes.

Your diagram is not include in the user's manual - where does it come from? Is you diagram more correct that the user's manual?

Thanks.

Regards

Mark

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NXP TechSupport
NXP TechSupport

Hi Mark Butcher ,

Thanks for your reply and let me clarify it
The PLL3 is in the power-down mode default after the MCU boots up, then the PLL3 must be bypassed. Either enable and set the PLL3 or bypass the PLL3 output by the PLL3 bypass clock selector.
1) where does it come from?
-- You can use the MCUXpresso Config Tools to review the clock distribution
https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools/mcuxpresso-co...
1) Is your diagram more correct that the user's manual?
-- In my opinion, the diagram can provide more detail information than the RM's.

Have a great day,
TIC

 

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Specialist V

Hi

Thanks again.

I believe that the situation is now clear:

1. The clock configuration helps in some ways in giving some clarity to what is in the user's manual although its representation is not necessarily fully accurate. For example there is actually no PLL3_BYPASS MUX as such:

pastedImage_1.png

Also, it allows the bypass to be set via PLL3_SW_CK_SEL (which dies exist) in a way that should - according to the user's manual - never be used.

2. The User's manual is missing a small but critical detail concerning the PLLs:

pastedImage_2.png

It only shows the (should never be used) bypass MUX, which is not selected(as indicated) after reset, but it doesn't show a second bypass control which is controlled in CCM_ANALOG_PLL_USB1. Rather than PLL3 supplying 480MHz by default it is powered down and the OSC_CLK bypass selected instead (the bit of information missing but the correct state according to the register's default setting).

3. Using CCM_CLKO1 and CCM_CLKO2 I could verify that the UART_CLK_ROOT is 4MHz out of reset due to this. Also I could confirm that with PLL3 powered up (and the bypass in CCM_ANALOG_PLL_USB1, which defaults to on,  removed) it increases to 80MHz.

I will be confirming all other default clocks as a subsequent exercise but expect that, respecting the missing PLL bypass, they will then all make full sense.

Regards

Mark