I want to get about 20000 16bit data from FPGA by frequency about 150MHz, i.e., I want to send them using SEMC in 133us, but when I check IMX Rt1064 evaluation board, I see that I can read from SDRAM by about 33MHz maximum frequency, i.e., I read for example 1000 16bit data from its SDRAM for about 30us!! Whereas I check and see about the 163MHZ frequency of the SDRAM clock on the oscilloscope. Would you please help me with how I can get 16-bit data from FPGA by 150MHZ frequency? If an alternative connection can be suggested (for example, gigabit ethernet or CSI or MIPI by IMX RT1170, please guide me). I send an image of the frequency specification of the SEMC for more detail.
Thank's a lot
The SEMC module is the way to go for what you are trying to achieve. You shouldn't have any problems with this implementation. How are you making the current tests to measure the performance of the SEMC module when reading the SDRAM?
Thank you for your reply. I check SEMC Performance, for example, by reading 1000 data (16bit) from SDRAM. By using example project in SDK, in other words, I set a GPIO to high before starting read from SDRAM and set it to low after reading is finished, and I see time length that this GPIO is high, for example, for 1000 sample this time is equal to about 30us. Before starting my PCB Design, I want to be sure I can send 20000 16bit samples from MY FPGA memory (the FPGA memory type can be considered synchronous SRAM) in less than or equal to 133us. In other words, I want to send every 16bit data in every SEMC clock edge, and I need this clock rate greater or equal to 150MHZ, and I need to send all 20000 data without any interrupt. I want to use SEMC in SDRAM Mode, but I am not sure. Please tell me:
1-Can you guarantee that this data transfer can be done by IMX RT1064 or RT1170 series?
What part did you prefer(RT1064or RT1170)?
2-Is SDRAM Mode is correct for this action, or should I use, for example, asynchronous SRAM Mode?
Thank you for your note.
Thanks for the additional information! I'm checking internally whether this is possible or not. I will give you an update as soon as possible.
You can't just send 20,000 transactions with no gaps in the data. First of all, none of the masters would send a transaction that large. The DMA is probably the most efficient way to move the data, but the largest DSIZE option in the DMA is 32-bytes. So the DMA maxes out at 16,16-bit accesses.
Then on the SEMC side, you also have to look at the burst size. For the SDRAMC the max burst length is 8 (SDRAMCR0[BL]). If you use the SRAM interface instead you can do up to a 64 beat burst (SRAMCR[BL]). But the actual burst size will also depend on the master too.
If their FPGA can support the synchronous SRAM interface, then that is probably the best option. The problem is that after every 16, 16-bit transactions there will be a gap for the DMA to complete its write cycle (it has to put the data it read somewhere), then the SEMC will resend the address for the SRAM and include any latency count clocks before the next 16, 16-bit data transactions on every single clock.
If they go to RT1170, then the big advantage is that the SDRAM interface can be 32-bits instead of 16, so that doubles the throughput. The max clock also goes to 200MHz. The SRAM interface isn't wider on RT1170, so while you can run it faster than on RT10xx, on RT1170 the SDRAM interface is probably the best option, but only if the FPGA can work with the 32-bit bus.
So technically the peak throughput can be what you want, the problem is that we can sustain that for anywhere near the 20k (or 10k with a 32-bit bus) that they want. We are going to have lots of gaps in between the bus cycles that will bring down the overall throughput to the point where it is nowhere near what you want. Pretty much any bus is going to have gaps between cycles and overhead that drag down the performance.
Thank You for the complete information. Based on your reply, I can find the maximum achievable transfer rate as below :
a) I should use the RT1170 series in SRAM 16bit mode and use DMA. My FPGA memory can support 32 bit wide and deliver output data in every clock edge with no limitation (Artix-7 block memory) (i attach timing diagram for more detail) but based on the diagram; it seems it can not support burst mode. I need a memory controller that can change the address for each data access. Can you say it is possible or not? If yes, what is the maximum transfer rate (including any latency)?