SPI using DMA with a Scatter/Gather (MIMXRT1020)

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SPI using DMA with a Scatter/Gather (MIMXRT1020)

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volkan_keles
Contributor I

We are facing the following problem when using the SPI in DMA (Slave) mode with Scatter/Gather.

We are filling 100 frames (each frame has 28 Bytes length) read from SPI SLAVE. And in another asynchronous timer callback, we occasionally get TCD[channel].DADDR destination address and evaluate the values written by the DMA. But we are having issues getting this destination address periodically. In a fixed 14.6 seconds period the destination address (TCD[channel].DADDR) returns a wrong value. By the way the 14.6 seems constant for each buffer size or read period configurations.

So far we couldn't find any solution for this issue. What might be the reason?

Thanks in advance

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3 Replies

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

Could you try the system application only with SPI slave working with eDMA module?

If in this application situation, there still has the same issue?


Have a great day,
Mike

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980 Views
volkan_keles
Contributor I

Hello,

seems like there is something like a dirty read. We have tried without SPI (edma scatter/gather example) and we observed the same issue periodically. Please try the code attached which is modified from the original driver examples (edma_scatter_gather.c) to see the issue.

We read TCD[channel].DADDR in an asynchronous loop (every 5ms), independent from the eDMA's loop. We guess that when we try to read DADDR while eDMA is changing its content (it is probably when at the end of TCD), we read a meaningless value.

We would be glad if you can address this issue, since it affects our application design decisions seriously. regards...

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980 Views
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi

First of all, really sorry for the delay reply.

During debug, I could find there with below eDMA TCD transfer configurations at SDRAM address: 0x81e00060 & 0x81e00040:

pastedImage_1.png

eDMA channel 0 will dynamic scatter/gather TCD configurations from SDRAM address: 0x81e00060 & 0x81e00040

pastedImage_2.png

From you tested code, the core will change source address value.

There could exists eDMA and core access SDRAM memory range at the same time, so it will arbitrated SDRAM access with NIC-301. Please set eDMA priority higher than core to access external SDRAM memory.

Thank you for the attention.

best regards,

Mike

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