SPI FIFO and Watermark

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SPI FIFO and Watermark

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suhel_mulla
Contributor III

Hello,

I am using i.MX RT1050 Evaluation Kit. I want to use SPI program in SDK for NXP i.MXRT 1052 processor. 

I am confused about the use FIFO and Watermark in SPI code. I haven't found any document which can explain these concepts. It is also not given in "i.MX RT1050 Processor Reference Manual".

Can you explain it here or suggest any document which explains the i.MX RT 1052 FIFO and watermark concepts in detail?

 

Thank you.

 
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suhel_mulla
Contributor III

Thank you for the explanation.

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suhel_mulla
Contributor III

Thank you for the explanation.

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi,

We don't have specific documents describing these concepts but I can help you explain this for you. A FIFO is a first in, first out internal stack that in this case will help you store SPI words. RT1050 has transmit FIFO of 16 words and a receive FIFO of 16 words.

On the other hand, watermarks can be used to generate interrupts depending on the number of words contained in these FIFOs. If the receive FIFO is greater than RXWATER value an interrupt will be generated, also if the number of words in the transmit FIFO is equal or less than TXWATER an interrupt will be fired.

Hope it helps!

Best regards,

Felipe

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