SEMC timing adjustments for SDRAM design with 2 chips

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SEMC timing adjustments for SDRAM design with 2 chips

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FMA
Contributor III

Hello,

Our design is based on an i.MX RT 1061 chip and uses two SDRAM chips (IS42S16160J similar to the one used on the EVKB board) sharing all SEMC pins except the CS0 and CSX1, in order to build a 32Meg x 16 interface.

We have initialized the SEMC interface with similar settings as those we used for the EVKB development board (except for the IOMUX, CSX and memory depth related settings) and, when basically used, everything works fine.

Now that we can run the interface we are applying u-boot's mtest routing to it and are finding that :

- from address 0x8200000 to 0x83FFFFFF (second chip configuration with CSX1) everything works well

- from addresss 0x80000000 to 0x81FFFFFF we are sometimes getting issues on some bits when the range of address tested by the mtest routing exceeds 32 kbytes. Indeed, when this happens, one or two bits (always the same) that the test expects to be set to 1 are set to 0. If we reduce the memory test range or do simple read / write operations to a given address, everything works fine.

On our board, the chip related to CS0 is located further away from the mimxrt106x processor than the second one. However, track lengths are matched for both chips (some tracks have a not perfectly matched length but only three have a relative length differing by 1.3%, one is around 0,2% and the rest falls below 0.03% of difference in length).

From the failing tests, I figured that something must be wrong when some of the bits of the bank address are changed, I tried to increase the below timing settings in order to accommodate for an additional clock cycle after ACTIVATE commmands but it does not seem to solve my issue.

The final values changed in comparison to those in EVKB are

- SDRAMCR1[ACT2RW] = 3

- SDRAMCR1[ACT2PRE] = 7 --> SDRAMCR1 = 0x00752932

- SDRAMCR2[ACT2ACT] = 1 -- > SDRAMCR2 = 0x00020920

 

Other SDRAM related settings are the following:

SDRAMCR0 = 0x00000F31

SDRAMCR4 = 0x50210A09

Any idea of what might be wrong with our design and the proper way to address this issue?

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1 Solution
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FMA
Contributor III

Hello,

Browsing through the forum I stubbled on this post: https://community.nxp.com/t5/i-MX-RT/i-MXRT1060-SEMC-SDRAM-Data-Corruption/m-p/1172919#M10887

 

The fix they mention seems to solve our issue (setting the BCMRx registers to 0x00000081.

I must confess that I do not understand how this works but it did.

I am still confused since the issue only appears if I set our design to use the 2 SDRAM chips and only when some of the bits of the bank address change and only with the chip corresponding to the lower address range ... . If I only activate one chip and got no corruption with the initial settings used ...

 

Anyways, it is fixed for us.

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432 Views
FMA
Contributor III

Hello,

Browsing through the forum I stubbled on this post: https://community.nxp.com/t5/i-MX-RT/i-MXRT1060-SEMC-SDRAM-Data-Corruption/m-p/1172919#M10887

 

The fix they mention seems to solve our issue (setting the BCMRx registers to 0x00000081.

I must confess that I do not understand how this works but it did.

I am still confused since the issue only appears if I set our design to use the 2 SDRAM chips and only when some of the bits of the bank address change and only with the chip corresponding to the lower address range ... . If I only activate one chip and got no corruption with the initial settings used ...

 

Anyways, it is fixed for us.

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