I captured some oscilloscope traces showing this.
1st capture below shows the unexpected behaviour on the scope, when the code reads from the SEMC interface I see 16 x CS# and 16 x OE#, when I expect just one. Top trace is CS#, bottom one OE#.
2nd capture below is the system working as expected, when the code reads from the SEMC interface I see on the scope one CS# pulse and one #OE pulse. The timebase is the same as above, 1us/div, so the scale is the same.
Last one is a zoom of the above, showing the 1 x CS# and 1 x OE#. The OE# pulse width is what I expected, 16 clocks of 163.86MHz = 98 ns.
Here is the code that sets up the clock source for the SEMC module (PLL2):
// Set the PLL2 PFD divider to ÷ 29,
// so the output frequency is now 528MHz * [18/29] = 327MHz
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
// Set PLL2 as the clock source for the SEMC module
CLOCK_SetMux(kCLOCK_SemcMux, 1);
// Set the AXI_PODF (a.k.a. SEMC_PODF) divider in CBCDR to ÷2,
// so the actual SEMC module clock is 327MHz ÷ 2 = 163.86MHz
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
InitSemc(); //NJWAnd lastly here is the contents of the InitSemc() function.
void InitSemc(void)
{
// enable SEMC clocks
CLOCK_EnableClock(kCLOCK_Semc);
CLOCK_EnableClock(kCLOCK_SemcExsc);
// initialise all the SEMC base registers to zero
SEMC->BR[0] = 0;
SEMC->BR[1] = 0;
SEMC->BR[2] = 0;
SEMC->BR[3] = 0;
SEMC->BR[4] = 0;
SEMC->BR[5] = 0;
// Base Register 6 (For PSRAM device 0) (BR6)
// High position 20 bits of SoC level Base Address = 0xA0000000;
// Memory size = 4 KB
// VALID = 1
SEMC->BR[6] = 0xa0000001;
SEMC->BR[7] = 0;
SEMC->BR[8] = 0;
// reset the SEMC module
SEMC->MCR = SEMC_MCR_SWRST_MASK;
while((SEMC->MCR & (uint32_t)SEMC_MCR_SWRST_MASK) != 0U)
{
;
}
// disable the SEMC module
SEMC->MCR |= SEMC_MCR_MDIS_MASK;
// setup register MCR, but keep the SEMC module disabled for now
// BTO = 0x1f
// DQSMD = 1
// MDIS = 1
SEMC->MCR = 0x1f000006;
// weight settings for ARM AXI bus memory access
// For now, values are taken from previous working SEMC example
SEMC->BMCR0 = 0x00104085;
SEMC->BMCR1 = 0x40602485;
// setup IOCR
// MUX_CSX0 = PSRAM CE#
SEMC->IOCR = 0x00000030;
// setup SRAMCR0
// Column Address bit width = 12 bits
// ADV# is high during address hold state
// ADV# is active low
// Address/Data MUX mode (ADMUX)
// Burst Length = 1
// ASYNC mode is enabled
// Port Size = 16 bits
SEMC->SRAMCR0 = 0x0000f001;
// setup SRAMCR1
// RE high time = 16 clocks of 163.86MHz = 98 ns
// RE low time = 16 clocks of 163.86MHz = 98 ns
// SEMC->SRAMCR1 = 0x66666633;
SEMC->SRAMCR1 = 0xffffffff;
// setup SRAMCR2
// CE# interval minimum time is 9 clock cycles
// Address to write data hold time is 6 clock cycles
// Turnaround time is 7 clock cycles
SEMC->SRAMCR2 = 0x08006600; //NEW, other bits should only apply to SYNC mode!
// SEMC->SRAMCR2 = 0x08f0660f; //OLD
// enable the SEMC module
SEMC->MCR &= ~SEMC_MCR_MDIS_MASK;
}I am struggling to explain this behaviour, what might be causing there to be 16x CS# and OE# pulses for one read?
This worked OK in an older version of software, so there must be a difference somewhere but I don't know where.
-Nick
