SAI4_MCLK source of IMXRT1170

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SAI4_MCLK source of IMXRT1170

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takayuki_ishii
Contributor IV

Hello community,

 

In Table 58-2. of the IMXRT1170 Reference Manual, SAI4 MCLK source is shown only SAI4_MCLK (pin).

Is SAI4_MCLK(pin) mean that clock source for SAI4 can use only external clock from SAI4_MCLK pin?

 

The other hand, SAI4_MCLK_DIR bit of GPR2 General Purpose Register, it can select input/output direction for SAI4_MCLK (12.4.4.4.3 Fields).

And Table 15-2. System Clocks Table inform about sai4_mclk_in2 and sai4_mclk_in3 but no more information about sai4_mclk_in2 and sai4_mclk_in3.

Is it possible to set a source other than external clock for SAI4_MCLK?

 

I look forward to hearing from you.

 

Best regards,

Ishii.

 

 

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jingpan
NXP TechSupport
NXP TechSupport

Hi @takayuki_ishii ,

Yes, it is confusing here.  Because in SDK demo, BOARD_BootClockRUN() calls CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg). And in clock config tools, it shows there are two SAI_MCLK. 

I tested on my RT1170 EVK. When select the SAI4_MCLK_DIR to 1 and GPIO_LPSR_05 as SAI4_MCLK output, I can see 24M signal on the pin. That means SAI4 has two MCLK source, SAI_MCLK1 and SAI_MCLK2. SAI4->TCR2[MSEL] can select which one will be used. And the SAI_MCLK1 is from SAI4_CLK_ROOT, SAI_MCLK2 is from external clock pin (GPIO_LPSR_05 or GPIO_LPSR_00).

Detail of the SAI4_CLK_ROOT can be got from clock config tool.

The table 58-2 is not correct. I'll report this issue.

jingpan_0-1645525963872.png

 

 

Regards,

Jing

 

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jingpan
NXP TechSupport
NXP TechSupport

Hi @takayuki_ishii ,

Yes, it is confusing here.  Because in SDK demo, BOARD_BootClockRUN() calls CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg). And in clock config tools, it shows there are two SAI_MCLK. 

I tested on my RT1170 EVK. When select the SAI4_MCLK_DIR to 1 and GPIO_LPSR_05 as SAI4_MCLK output, I can see 24M signal on the pin. That means SAI4 has two MCLK source, SAI_MCLK1 and SAI_MCLK2. SAI4->TCR2[MSEL] can select which one will be used. And the SAI_MCLK1 is from SAI4_CLK_ROOT, SAI_MCLK2 is from external clock pin (GPIO_LPSR_05 or GPIO_LPSR_00).

Detail of the SAI4_CLK_ROOT can be got from clock config tool.

The table 58-2 is not correct. I'll report this issue.

jingpan_0-1645525963872.png

 

 

Regards,

Jing

 

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takayuki_ishii
Contributor IV

Hello @jingpan 

 

Thank you for your evaluation work..

 

I understand that SAI4_MCLK1 can use intanal clock as SAI4 clock source.

And The table 58-2 is not correct.

 

I will  update this information to customer.

 

Best regards,

Ishii.

 

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