RT1170 watchdog

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RT1170 watchdog

Contributor I

I have implemented system watchdog 1 on the RT1176 and enabled the WDT bit so that the WDOG_B signal is asserted. I see some different behavior than what is described in the reference manual and the info in the doc is also not entirely clear. I need some help to identify what happens when the watchdog trigger.

  1. The doc ( states that:
    - WDOG timeout condition will assert the WDOG_B until a POR occurs.
    - WDOG power-down counter timeout will only assert the WDOG_B for one clock cycle Is this correct?
  2. Chapter 78.4 say that the WDOG_B signal will power down the chip. Everywhere else this is not mentioned. What happens when the WDOG_B signal is asserted?
    - If the chip is powered down on WDOG_B assert, do this mean that the chip will automatically reset from POR?
    - If the chip reset from POR on WDOG_B assert, how is it possible to detect if the watchdog was the cause of the reset (as POR is one of the options in WRSR)?
  3. Figure 78-4 in the doc show that the WDOG_B signal go low when asserted. Is this correct? (we measure the signal to go high...)
  4. What parts of the chip is reset on a POR? Registers? RAM? Peripherals?
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NXP TechSupport
NXP TechSupport

Hi @stekre,

1. Yes, this is correct.

2. What Chapter 78.4 means by this is that it can be used when routed externally. For example, looking into the MIMXRT1170-EVK schematic, we can see that the WDOG_B output signal from the RT1170 is used to disable U39, which provides 3.3V for the whole system. In this way, the WDOG_B signal is used to cause a POR of the chip externally. 

3. We expect and signal with a "_B" suffix to go low when asserted.

4. As it is mentioned on Section "25.3.4 Reset behavior of the Power-on Reset", all of the chip is reset except the SNVS block.




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