RT1064 RT1050 Increase internal RAM (OCRAM, ITCM, DTCM) in linker

[karl_fraasch]

Hello, I am trying to increase the internal RAM in the linker file in order to support a larger .text region. The sample applications all allocate the following in the linker file for text region.

define symbol m_text_start = 0x00000400;
define symbol m_text_end = 0x0001FFFF;

I am trying to understand how this can be increased in order that the text region can support up to 512kB

On the RT1064, I understand there is 1MB of internal ram available distributed as follows,

OCRAM, ITCM, DTCM: 512kB

Reserved OCRAM: 512kB

Can anybody provide some insight on a good approach to this?

Pasting IAR linker script included with SDK for reference.

/*
** ###################################################################
** Processors: MIMXRT1064CVJ5A
** MIMXRT1064CVL5A
** MIMXRT1064DVJ6A
** MIMXRT1064DVL6A
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1064RM Rev.0.1, 12/2018 | IMXRT1064SRM Rev.3
** Version: rev. 0.1, 2018-06-22
** Build: b191015
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/

define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003FF;

define symbol m_text_start = 0x00000400;
define symbol m_text_end = 0x0001FFFF;

define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;

define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x202BFFFF;

/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
 define symbol __size_cstack__ = __stack_size__;
} else {
 define symbol __size_cstack__ = 0x0400;
}

if (isdefinedsymbol(__heap_size__)) {
 define symbol __size_heap__ = __heap_size__;
} else {
 define symbol __size_heap__ = 0x0400;
}

define exported symbol __NCACHE_REGION_START = m_data2_start;
define exported symbol __NCACHE_REGION_SIZE = 0x0;

define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;

define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
 | mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];

define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };

initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };

place at address mem: m_interrupts_start { readonly section .intvec };

place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in CSTACK_region { block CSTACK };

[jeremyzhou]

Hi Karl Fraasch,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
It not only needs to update the linker file but also modify the configuration of FlexRAM, and I'd like to suggest you to learn how to configure the FlexRAM by referring to the AN12077.

Have a great day,
TIC

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