RT1060 - use of OCRAM breaks fatfs example

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RT1060 - use of OCRAM breaks fatfs example

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tmeyer1
Contributor III

I'm working on a FreeRTOS project and plan to use all 1MB of the internal RAM on the RT1060. I've noticed that there is a change in the code behavior based off the location I store the global data.

For example, currently I'm working with the RT1060EVK board with a uSD card and FatFS. I import the example project: evkmimxrt1060_sdcard_fatfs_freertos and change only one setting, which breaks the example. Out of the box, it run as expected. After moving the global data into the OCRAM (from DTCM), the application no longer writes to the SD card.

pastedImage_1.png

Can anyone explain to me what I'm missing, and why changing this from SRAM_OC to SRAM_DTC fixes some issues in the SD initialization. 

FYI: the output from the example when it fails is as follows:

SDCARD fatfs freertos example.

Card inserted.

Make file system......The time may be long if the card capacity is big.
Make file system failed.

The example I am running is from SDK version 2.6.2.

Thanks,

Tim

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Takashi_Kashiwagi
Senior Contributor I

Hi Tim-san

Did you change MPU setting?

In Default Setting, OCRAM area is set to not shareable by BOARD_ConfigMPU. 

So transfer using DMA does not work.

/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);

/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);

Best Regards,

T.Kashiwagi

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jingpan
NXP TechSupport
NXP TechSupport

Hi Tim,

This is because OCRAM default is cacheable. Since some SD control block in RAM is shared by SD peripheral and MCU, cache function cause data missing. When MCU write something to the block, it only write to cache actually. Peripheral can get it. When peripheral write something to the block, MCU also don't know. Because it only read from cache actually.

TCM is not cacheable. So, it hasn't this problem. For i.MXRT, shareable means non-cacheable by default. T.Kashiwagi's method can resolve the problem.

Regards,

Jing

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tmeyer1
Contributor III

Perfect, thanks so much for pointing that out. It all makes sense to me know. 

Thanks,

Tim

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545 Views
Takashi_Kashiwagi
Senior Contributor I

Hi Tim-san

Did you change MPU setting?

In Default Setting, OCRAM area is set to not shareable by BOARD_ConfigMPU. 

So transfer using DMA does not work.

/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);

/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);

Best Regards,

T.Kashiwagi

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