RT1060 SEMC PSRAM CLK

[SSZHH]

RT1060 RM shows that the CLK of SEMC SDRAM is continuously generated, regardless of whether CS takes effect.But the CLK of SRAM in SYNC mode is only generated when CS is low. Is the actual situation the same as described in the Figure 25-63? SRAM interface will not generate CLK when CS is high?

[Omar_Anguiano]

Hello
Hope you are well.

You´re correct, the SEMC CLK will behave as the figures describe.

If you have more questions do not hesitate to ask me.
Best regards,
Omar

[SSZHH]

Hi Omar

thanks for your reply.

I have validated SEMC SRAM SYNC mode behavior in RT1064 too, it's indeed the same as the figures describe. But I noticed that SEMC CLK disappear after latency count when SEMC reads. if SEMC reads more data in one burst, the last CLK also disappears. The SEMC CLK count is correct when it writes. I want to know if this behavior is normal?

Best regards!

[Omar_Anguiano]

Hello
The CLK should not disappear when reading. There might be an issue with your device or the SEMC configuration.
It will be helpful if you share your SEMC configuration as well as the part number of the memory you are using.

If you have more questions do not hesitate to ask me.
Best regards,
Omar

[SSZHH]

Hello

The SEMC basic configuration is default.

The SEMC SRAM configuration is as follows.

The RT1060 doesn't connect to external memory, I just want to know SEMC PSRAM behavior.

Best regards!

[Omar_Anguiano]

It´s hard to tell that this is an expected behavior while no PSRAM memory is connected to the module. The default configuration seems correct but this may vary across different memories.
To check that the read behavior of the module is correct you need to connect a memory to the module.

If you have more questions do not hesitate to ask me.
Best regards,
Omar