RT1052: Unclarity in pixel clock configuration of lvgl_demo

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RT1052: Unclarity in pixel clock configuration of lvgl_demo

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airios_arno
Contributor II

I'm currently evaluating the iMXRT1052, using the MIMXRT1050-EVK / EVKBIMXRT1050 and the LCD panel.

I've imported the lvgl_demo_benchmark_bm and lvgl_demo_widgets_bm examples from the MCUXpresso SDK.

In both examples, I noticed that the function DEMO_InitLcdClock (in board/lvgl_support.c) is used to configure the pixel clock, but I can't explain the factor 10 difference between the wanted pixel clock frequency (9.3 MHz) and the Video PLL configuration (93.0 MHz). Can someone elaborate where this factor 10 is coming from

static void DEMO_InitLcdClock(void)
{
    /*
     * The desired output frame rate is 60Hz. So the pixel clock frequency is:
     * (480 + 41 + 4 + 18) * (272 + 10 + 4 + 2) * 60 = 9.2M.
     * Here set the LCDIF pixel clock to 9.3M.
     */

    /*
     * Initialize the Video PLL.
     * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
     */
    clock_video_pll_config_t config = {
        .loopDivider = 31,
        .postDivider = 8,
        .numerator   = 0,
        .denominator = 0,
    };

    CLOCK_InitVideoPll(&config);

    /*
     * 000 derive clock from PLL2
     * 001 derive clock from PLL3 PFD3
     * 010 derive clock from PLL5
     * 011 derive clock from PLL2 PFD0
     * 100 derive clock from PLL2 PFD1
     * 101 derive clock from PLL3 PFD1
     */
    CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);

    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4);

    CLOCK_SetDiv(kCLOCK_LcdifDiv, 1);
}

 

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jeremyzhou
NXP Employee
NXP Employee

Hi,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Just as the below shows, the CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4) is used to set the LCDIF_PRED, and CLOCK_SetDiv(kCLOCK_LcdifDiv, 1)is used to set the LDIF_PODF.
The total divisor will be (4+1)*(1*1) = 10, after through the divider, the clock became 9.3 MHz。

jeremyzhou_0-1652435963695.png

 


Have a great day,
TIC

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1 Reply
837 Views
jeremyzhou
NXP Employee
NXP Employee

Hi,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Just as the below shows, the CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4) is used to set the LCDIF_PRED, and CLOCK_SetDiv(kCLOCK_LcdifDiv, 1)is used to set the LDIF_PODF.
The total divisor will be (4+1)*(1*1) = 10, after through the divider, the clock became 9.3 MHz。

jeremyzhou_0-1652435963695.png

 


Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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