RT1051: QTIMER configured as PWM

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RT1051: QTIMER configured as PWM

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mastupristi
Senior Contributor I

On an RT1051 I use QTIMERS to make PWM signals.

I need that when I set 0 to duty the output stays low, while if I set 100 it stays high.

I have tried by modifying the SDK example by imposing

 

QTMR_SetupPwm(BOARD_QTMR_BASEADDR, BOARD_QTMR_PWM_CHANNEL, QTMR_PWM_OUTPUT_FREQUENCY, 0, false, QTMR_SOURCE_CLOCK);

 

or

 

QTMR_SetupPwm(BOARD_QTMR_BASEADDR, BOARD_QTMR_PWM_CHANNEL, QTMR_PWM_OUTPUT_FREQUENCY, 100, false, QTMR_SOURCE_CLOCK);

 

but I cannot get the desired result

 

how can i get what i want?

 

best regards

Max

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

if I understand correctly there is no way to avoid glitches when I set duty 0% or 100%, right?

>>>>Yes, no way to avoid the glitch for the 0% or 100% percent. As a workaround, if you do not want any glitch, in the application code, when  the duty cycle is 0% or 100%, you can set the pad as GPIO output mode and output low or high.

BR

XiangJun Rong

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

The 100% percent and 0% percent are extreme examples, if you use the other percent for example from 1% to 99%, is the PWM duty cycle okay?

The  QTMR_SetupPwm()  uses the variable-Frequency  PWM mode, the TMR_COMP1 represents the PWM LOW logic time, the TMR_COMP2 represents the PWM high logic time(dependent on plarity of PWM signal).

The PWM period value is QTMR_SOURCE_CLOCK/QTMR_PWM_OUTPUT_FREQUENCY, the TMR_COMP2 represents the high time, it is (duty cycle percent)*QTMR_SOURCE_CLOCK/QTMR_PWM_OUTPUT_FREQUENCY.

The TMR_COMP1 represents the LOW time, it is (1-duty cycle percent)*QTMR_SOURCE_CLOCK/QTMR_PWM_OUTPUT_FREQUENCY.

For the extreme duty cycle 0% and 100%, one of the TMR_COMP1 or TMR_COMP2 is zero, do you see glitch or whatever?

For detailed information, pls refer to section 46.6.5.14 Variable-Frequency PWM Mode in IMXRT1050RM.pdf

 

BR

XiangJun Rong

 

 

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mastupristi
Senior Contributor I

if you use the other percent for example from 1% to 99%, is the PWM duty cycle okay?

Yes

 

For the extreme duty cycle 0% and 100%, one of the TMR_COMP1 or TMR_COMP2 is zero, do you see glitch or whatever?

Yes

 

so if I understand correctly there is no way to avoid glitches when I set duty 0% or 100%, right?

 

best regards

Max

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911 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

if I understand correctly there is no way to avoid glitches when I set duty 0% or 100%, right?

>>>>Yes, no way to avoid the glitch for the 0% or 100% percent. As a workaround, if you do not want any glitch, in the application code, when  the duty cycle is 0% or 100%, you can set the pad as GPIO output mode and output low or high.

BR

XiangJun Rong

 

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