Questions when using SDRAM and SRAM together on SEMC

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Questions when using SDRAM and SRAM together on SEMC

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george
Senior Contributor I

Hi all,

My customer wants to use the RT117x SEMC with SDRAM and SRAM-I/F.
SRAM-I/F connect to a FPGA with ASYNC non-ADMUX w/ WAIT.

During a long burst-type DMA transfer between the FPGA and a memory area, is the DMA transfer interrupted to insert a refresh cycle for SDRAM if the transfer period is longer than the SDRAM refresh cycle?
If so, will DMA transfers resume automatically after inserting a refresh cycle?

Please introduce some suitable material.

Best Regards,
George

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PhilP
Contributor I

This is interesting, as my application architecture is probably going to be exactly the same as George's (FPGA -> external SDRAM via DMA). I'm currently experimenting with the MIMXRT1170-EVK evaluation kit, to prove that I can use DMA to copy form one external SDRAM address to another and to get some timings.

I have combined two of the demos (SEMC and EDMA), and this works fine for internal to internal memory and external to internal, but if I change the destination address to external and try to copy from internal to external, it doesn't work. The interrupt is hit to say that it's finished, there are no errors, and the time taken is longer, so it looks like it should have worked. But when I print out the contents of the destination addresses, nothing has changed.

I am just using the default settings from the SEMC demo, and the only thing I have changed in the EDMA demo code is the destination address and number of bytes to be transferred, so I can't see anything that is obviously wrong. Any pointers to what I could be missing?

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

Hello

Hope you are well. I apologize for my delayed reply.
REBL field states that SEMC can send multiple auto-refresh commands in one burst if this field is set to a non-zero value. When this field is 0 the auto-refresh will be inserted once.
The eDMA has the feature of suspending a DMA channel, I suggest you to refer chapter 6.4.8.1 of the reference manual.

Let me know if this information is helpful, if you have more questions do not hesitate to ask me.
Best regards,
Omar

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george
Senior Contributor I

Dear @Omar_Anguiano 

Thank you for your reply.

If there is a conflict with the refresh for SDRAM during a DMA transfer as shown in the figure below, does the DMA controller automatically interrupt the transfer and perform a refresh for SDRAM?
Or it may be done by SEMC.

PRI_20210928-161417.bmp

Best Regards,
George

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

I apologize for my delayed reply.
Apparently, to avoid any issue you need to suspend the DMA transfer to insert a refresh to the SDRAM. Otherwise the refresh will be inserted once the transfer is complete.
I´m consulting this internally so I can give more detailed answer, I will reply you as soon as possible.

If you have more questions do not hesitate to ask me.
Best regards,
Omar
 

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

After one transaction completes, SEMC can automatically insert auto-refresh command between two burst access, even if there is more burst access and trigger back-to-back access on SDRAM, SEMC still can interrupt access and insert auto-refresh command. 

One DMA transaction will split many burst operations on SEMC side based on SEMC burst size setting, and auto-refreshing command can insert between SEMC burst access.

If you have more questions do not hesitate to ask me.
Best regards,
Omar

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george
Senior Contributor I

Hello @Omar_Anguiano,

Thank you for answering.

Please tell me one last thing.
In other words, SEMC has overall control over the contention between SDRAM refresh and SRAM access, so can we interpret it as something that users don't need to be aware of?

BR,
George

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

Hello

I won´t describe the SEMC as something that the user doesn´t need to be aware of. It is true that the refresh command is handled by the module and it will be inserted automatically between SEMC burst access.

Let me know if you have more questions.
Best regards,
Omar

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george
Senior Contributor I

Hello @Omar_Anguiano,

Sorry for my late reply.

It seems that my expression was incorrect.
Is our understanding correct below?

  1. One DMA transaction from external SRAM to internal RAM splits many burst operations on the SEMC side based on the SEMC burst size setting, and auto-refresh command for SDRAM are automatically inserted during SEMC burst access.
  2. Users do not have to manage arbitration on the SEMC bus, pending and resume for DMA, and auto-refresh command insertion for SDRAM.

BR,
George

 

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

1. The SDRAM refresh command is inserted between SEMC burst access.

2. You are correct. The DMA operation will be split in multiple burst access by the SEMC side based on the burst size setting and auto-refresh is automatically inserted.

If you have more questions do not hesitate to ask me.
Best regards,
Omar

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george
Senior Contributor I

Hello @Omar_Anguiano 

I would like your comments on the case I have shown above.

BR,
George

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