Problem with eight bit SRAM SEMC interface RT1020

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Problem with eight bit SRAM SEMC interface RT1020

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tmerics
Contributor I

I'm trying to implement an 8 bit SRAM interface on the SEMC with a modified RT1020EVK. I have it configured for 4K of memory. I am using the following SRAM config:

    sram.cePinMux           = kSEMC_MUXCSX0;
    sram.addr27             = kSEMC_MORA27_NONE;
    sram.address            = SRAM_ADDR;
    sram.memsize_kbytes     = 4 * 1024;
    sram.advActivePolarity  = kSEMC_AdvActiveLow;                // kSEMC_AdvActiveLow         kSEMC_AdvActivehigh
    sram.addrMode           = kSEMC_AdvAddrdataMux;                // kSEMC_AddrDataMux        kSEMC_AdvAddrdataMux
    sram.burstLen           = kSEMC_Sdram_BurstLen1;
    sram.portSize           = kSEMC_PortSize8Bit;                // kSEMC_PortSize8Bit        kSEMC_PortSize16Bit

with the pin config:

/*
 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
  - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, open_drain: Disable}
  - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, open_drain: Disable}
  - {pin_num: '18', peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '17', peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '16', peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '15', peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '14', peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '13', peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '12', peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '10', peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '1', peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_14, slew_rate: Fast, open_drain: Disable, speed: MHZ_200, drive_strength: R0_4, pull_keeper_enable: Disable}
  - {pin_num: '129', peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_27}
  - {pin_num: '130', peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_26}
  - {pin_num: '91', peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_AD_B1_01}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
 */

The upper 4 address bits (11-8) are always zero. I cannot seem to find any information on the advanced MUX mod to help understand the problem. If I use normal mux mode I do not get the second ADV signal for the upper address lines.

Attached is a screen shot from my logic analyzer:
Yellow trace        chip select
1          ADV
2          OE
3          WE
4          A/D0
5          A/D1
6          A/D2
7          A/D3
It is a write to location 0xFFE. The lower 8 address lines work fine. I can never get any of the upper address lines to work. I have also looked at the upper four bit of the address and get the same results.
Is there any information on implementing an 8 bit interface on SEMC?
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8 Replies

157 Views
tmerics
Contributor I

Forgot to mention the SRAM address is 0xA0000000.

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157 Views
jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Thomas Merics,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Before answering your question, I was wondering if you can tell me which SRAM chip you use and share the schematic about the SRAM connection.
Looking forward to your reply.

Have a great day,
TIC

 

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157 Views
tmerics
Contributor I

I have modified an RT1020EVK. Basically I have removed the sdram and put test points on the signals I want to observe. There is no SRAM installed on the board. THe RT1020 doesn't know that and should still generate the correct control signals. I have test points on the following:

D0 - D7 (GPIO_EMC_0 - GPIO_EMC_7)

D8 - D15 (GPIO_EMC_32 - GPIO_EMC_39)

CSX0 GPIO_AD_B1_01

WE GPIO_EMC_26

OE GPIO_EMC_27

ADV GPIO_EMC_14

WE, OE, ADV, CSX0 all work as in the timing diagrams. I get the correct value on D0-D7 on the second ADV signal. D0-D7 are always zero on the first adv.

I tried using a 16 bit bus with normal A/D multiplexing and I get the correct values on D0 - D11.

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Thomas Merics,

Thanks for your reply.
According to your introduction, you need to read the D8~D11, it should set the sram.portSize = kSEMC_PortSize16Bit instead of kSEMC_PortSize8Bit.

Have a great day,
TIC

 

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tmerics
Contributor I

How does the eight bit port size work? What is the maximum memorey size which can be accessed with the eight bit mode? Why are there two adv signals to latch the address? With the 16 bit two accesses are done to address a 32 bit memory. What is the difference between AD Mux and advanced AD mux modes? 4K of memory is the minimum amount. What happens when there is more than 64K are there more adv signals to latch the larger address?

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Thomas Merics,

Thanks for your reply.
1) What is the maximum memory size which can be accessed with the eight-bit mode?
-- 4 Mb.
2) Why are there two adv signals to latch the address?
-- It seems a bit weird, and whether you can share the complete configuration of the SRAM struct.
I've checked with some Parallel SRAMs whose port size is 8, I find most of them don't have the ADV pin in their package. In another word, the ADV pin is not necessary to participate in the read or write SRAM operation.
3) What is the difference between AD Mux and advanced AD mux modes?
-- I'll contact the AE and reply to you later.

Have a great day,
TIC

 

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tmerics
Contributor I

Isn't the ADV signal basically used to latch the address lines since they are presented on the same eight lines as the data? It would control the parts used to hold the address that is presented to the SRAM chip.

The timing diagrams are 24-58 and 24-61 in the RT1064 reference manual.

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jeremyzhou
NXP TechSupport
NXP TechSupport

HiThomas Merics,

Thanks for your reply.
1) Isn't the ADV signal basically used to latch the address lines since they are presented on the same eight lines as the data?
-- Yes, if the address and data line is shared.
Note: AD Mux mode, the address width is 16, and the address width can exceed the 16 after setting advanced AD mux mode.

Have a great day,
TIC

 

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