MIMXRT1051CVL5B manual for LPSPI

[stefan_waldschm]

Hi,

I need to write the necessary code to adapt a third-party library to the LPSPI of an "MIMXRT1051CVL5B".

I was using this document https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf "MXRT1050RM Rev. 1, 03/2018" but experienced several deviations between the PDF and my silicon.

Example:

* Version ID Register should read 1.2 (according to

https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf#d9351e289a1310), but mine says 1.1.

* PCSNUM in Parameter Register (PARAM) should be 4 according to https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf#d9351e576a1310, but mine says 0.

Therefore, I assume I am using the wrong documentation. Can anyone please lead me to the correct documentation for my silicon?

Thanks a lot

stefan

[TomE]

Stefan, do you have NXP's Sample Code for the LPSPI?

I detailed where it is in my answer to this post:

https://community.nxp.com/message/1086389

The LPSPI driver is in the path:

SDK_2.4.2_EVKB-IMXRT1050/devices/MIMXRT1052/drivers/fsl_lpspi.c

This source file has 1851 lines in it, so there's a lot of code that might help with your code development.

The "LPSPI_MasterSetBaudRate()" function can do with rewriting. It works through the 8 different Prescaler values and the 256 scaler values, and tries EVERY POSSIBLE COMBINATION before picking the "best". That's 2048 baud rate calculations to avoid doing what amounts to one scaling check and one divide. That whole thing takes 96 MICROSECONDS to calculate on a CPU running at the maximum clock rate.

If you're only setting the speed once, then that isn't a problem. If you're using multiple SPI devices running at different speeds on the same or different chip selects, you'll be switching baud rates between transfers all the time.

That existing function also picks a rate that severely limits the CS to CS delays that are available. I fixed that (so I could get 10MHz and a 2.2us chip select delay) and had it exit on first match, and the function now runs 150 times faster.

Tom

[AldoG]

Hello Stefan,

The Reference Manual you're using should be the correct one Rev. 1, 

the deviations you found were already reported and are undergoing some test,
this will be reported and hopefully will be corrected on the releasing of a new version of the Reference Manual 
Thank you!

Best regards,
Aldo.

[TomE]

Mine too.

I have to new IMXRT1050-EVKB boards. Both have "MIMXRT1052" CPUs on them coded "DVL6B  iN04V  CTAA1803A", and the four LPSPI registers show:

(gdb) x/2x 0x403a0000
0x403a0000:    0x01010004    0x00000404
(gdb) x/2x 0x40394000
0x40394000:    0x01010004    0x00000404
(gdb) x/2x 0x40398000
0x40398000:    0x01010004    0x00000404
(gdb) x/2x 0x4039c000
0x4039c000:    0x01010004    0x00000404
(gdb) x/2x 0x403a0000
0x403a0000:    0x01010004    0x00000404

Decoded, that's the same as Stefan sees. The silicon is version "1.1" where the documentation is for "1.2". As well, the second register in the Reference Manual says the chip supports FOUR PCS Chip Select pins, while the register read from the chip says it supports ZERO PCS chip select pins. Or maybe V1.1 didn't set this field and only V1.2 does.

It's at this time I usually resort to "Archaeology" to see where the various manuals and chip modules have been cut-and-pasted from. The RT1050, RT1060 and RT1020 manuals all agree (V1.2). "LPSPI" also turns up in the KL28. That chip has LPSPI Version "V1.0" and the "Parameter Register" doesn't have the PCSNUM field. The "S32K1xx Series" manual is the same.

So what are the differences between V1.0 (documented and in released chips), V1.1 (in the chips we have) and V1.2 (in the documents and not in the chips)?

Tom